diff options
author | Alan Cox <alan@linux.intel.com> | 2011-11-03 14:22:04 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2011-11-16 06:26:35 -0500 |
commit | 5c49fd3aa0ab025e5f94617249db10a33138f37b (patch) | |
tree | d0199b52770ef27685dd0e2e7ec32b8fc8550e91 /drivers/gpu/drm/gma500/psb_irq.c | |
parent | 5091b7eb3f90a0aa5bb4f265b8427782539342c2 (diff) |
gma500: Add the core DRM files and headers
Not really a nice way to split this up further for submission. This
provides all the DRM interfacing logic, the headers and relevant glue.
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/gma500/psb_irq.c')
-rw-r--r-- | drivers/gpu/drm/gma500/psb_irq.c | 553 |
1 files changed, 553 insertions, 0 deletions
diff --git a/drivers/gpu/drm/gma500/psb_irq.c b/drivers/gpu/drm/gma500/psb_irq.c new file mode 100644 index 000000000000..2d9545816b54 --- /dev/null +++ b/drivers/gpu/drm/gma500/psb_irq.c | |||
@@ -0,0 +1,553 @@ | |||
1 | /************************************************************************** | ||
2 | * Copyright (c) 2007, Intel Corporation. | ||
3 | * All Rights Reserved. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it | ||
6 | * under the terms and conditions of the GNU General Public License, | ||
7 | * version 2, as published by the Free Software Foundation. | ||
8 | * | ||
9 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
12 | * more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License along with | ||
15 | * this program; if not, write to the Free Software Foundation, Inc., | ||
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
17 | * | ||
18 | * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to | ||
19 | * develop this driver. | ||
20 | * | ||
21 | **************************************************************************/ | ||
22 | /* | ||
23 | */ | ||
24 | |||
25 | #include <drm/drmP.h> | ||
26 | #include "psb_drv.h" | ||
27 | #include "psb_reg.h" | ||
28 | #include "psb_intel_reg.h" | ||
29 | #include "power.h" | ||
30 | |||
31 | /* | ||
32 | * inline functions | ||
33 | */ | ||
34 | |||
35 | static inline u32 | ||
36 | psb_pipestat(int pipe) | ||
37 | { | ||
38 | if (pipe == 0) | ||
39 | return PIPEASTAT; | ||
40 | if (pipe == 1) | ||
41 | return PIPEBSTAT; | ||
42 | if (pipe == 2) | ||
43 | return PIPECSTAT; | ||
44 | BUG(); | ||
45 | } | ||
46 | |||
47 | static inline u32 | ||
48 | mid_pipe_event(int pipe) | ||
49 | { | ||
50 | if (pipe == 0) | ||
51 | return _PSB_PIPEA_EVENT_FLAG; | ||
52 | if (pipe == 1) | ||
53 | return _MDFLD_PIPEB_EVENT_FLAG; | ||
54 | if (pipe == 2) | ||
55 | return _MDFLD_PIPEC_EVENT_FLAG; | ||
56 | BUG(); | ||
57 | } | ||
58 | |||
59 | static inline u32 | ||
60 | mid_pipe_vsync(int pipe) | ||
61 | { | ||
62 | if (pipe == 0) | ||
63 | return _PSB_VSYNC_PIPEA_FLAG; | ||
64 | if (pipe == 1) | ||
65 | return _PSB_VSYNC_PIPEB_FLAG; | ||
66 | if (pipe == 2) | ||
67 | return _MDFLD_PIPEC_VBLANK_FLAG; | ||
68 | BUG(); | ||
69 | } | ||
70 | |||
71 | static inline u32 | ||
72 | mid_pipeconf(int pipe) | ||
73 | { | ||
74 | if (pipe == 0) | ||
75 | return PIPEACONF; | ||
76 | if (pipe == 1) | ||
77 | return PIPEBCONF; | ||
78 | if (pipe == 2) | ||
79 | return PIPECCONF; | ||
80 | BUG(); | ||
81 | } | ||
82 | |||
83 | void | ||
84 | psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) | ||
85 | { | ||
86 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | ||
87 | u32 reg = psb_pipestat(pipe); | ||
88 | dev_priv->pipestat[pipe] |= mask; | ||
89 | /* Enable the interrupt, clear any pending status */ | ||
90 | if (gma_power_begin(dev_priv->dev, false)) { | ||
91 | u32 writeVal = PSB_RVDC32(reg); | ||
92 | writeVal |= (mask | (mask >> 16)); | ||
93 | PSB_WVDC32(writeVal, reg); | ||
94 | (void) PSB_RVDC32(reg); | ||
95 | gma_power_end(dev_priv->dev); | ||
96 | } | ||
97 | } | ||
98 | } | ||
99 | |||
100 | void | ||
101 | psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) | ||
102 | { | ||
103 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | ||
104 | u32 reg = psb_pipestat(pipe); | ||
105 | dev_priv->pipestat[pipe] &= ~mask; | ||
106 | if (gma_power_begin(dev_priv->dev, false)) { | ||
107 | u32 writeVal = PSB_RVDC32(reg); | ||
108 | writeVal &= ~mask; | ||
109 | PSB_WVDC32(writeVal, reg); | ||
110 | (void) PSB_RVDC32(reg); | ||
111 | gma_power_end(dev_priv->dev); | ||
112 | } | ||
113 | } | ||
114 | } | ||
115 | |||
116 | void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe) | ||
117 | { | ||
118 | if (gma_power_begin(dev_priv->dev, false)) { | ||
119 | u32 pipe_event = mid_pipe_event(pipe); | ||
120 | dev_priv->vdc_irq_mask |= pipe_event; | ||
121 | PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); | ||
122 | PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); | ||
123 | gma_power_end(dev_priv->dev); | ||
124 | } | ||
125 | } | ||
126 | |||
127 | void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe) | ||
128 | { | ||
129 | if (dev_priv->pipestat[pipe] == 0) { | ||
130 | if (gma_power_begin(dev_priv->dev, false)) { | ||
131 | u32 pipe_event = mid_pipe_event(pipe); | ||
132 | dev_priv->vdc_irq_mask &= ~pipe_event; | ||
133 | PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); | ||
134 | PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); | ||
135 | gma_power_end(dev_priv->dev); | ||
136 | } | ||
137 | } | ||
138 | } | ||
139 | |||
140 | /** | ||
141 | * Display controller interrupt handler for vsync/vblank. | ||
142 | * | ||
143 | */ | ||
144 | static void mid_vblank_handler(struct drm_device *dev, uint32_t pipe) | ||
145 | { | ||
146 | drm_handle_vblank(dev, pipe); | ||
147 | } | ||
148 | |||
149 | |||
150 | /** | ||
151 | * Display controller interrupt handler for pipe event. | ||
152 | * | ||
153 | */ | ||
154 | #define WAIT_STATUS_CLEAR_LOOP_COUNT 0xffff | ||
155 | static void mid_pipe_event_handler(struct drm_device *dev, uint32_t pipe) | ||
156 | { | ||
157 | struct drm_psb_private *dev_priv = | ||
158 | (struct drm_psb_private *) dev->dev_private; | ||
159 | |||
160 | uint32_t pipe_stat_val = 0; | ||
161 | uint32_t pipe_stat_reg = psb_pipestat(pipe); | ||
162 | uint32_t pipe_enable = dev_priv->pipestat[pipe]; | ||
163 | uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16; | ||
164 | uint32_t i = 0; | ||
165 | |||
166 | spin_lock(&dev_priv->irqmask_lock); | ||
167 | |||
168 | pipe_stat_val = PSB_RVDC32(pipe_stat_reg); | ||
169 | pipe_stat_val &= pipe_enable | pipe_status; | ||
170 | pipe_stat_val &= pipe_stat_val >> 16; | ||
171 | |||
172 | spin_unlock(&dev_priv->irqmask_lock); | ||
173 | |||
174 | /* clear the 2nd level interrupt status bits */ | ||
175 | /** | ||
176 | * FIXME: shouldn't use while loop here. However, the interrupt | ||
177 | * status 'sticky' bits cannot be cleared by setting '1' to that | ||
178 | * bit once... | ||
179 | */ | ||
180 | for (i = 0; i < WAIT_STATUS_CLEAR_LOOP_COUNT; i++) { | ||
181 | PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg); | ||
182 | (void) PSB_RVDC32(pipe_stat_reg); | ||
183 | |||
184 | if ((PSB_RVDC32(pipe_stat_reg) & pipe_status) == 0) | ||
185 | break; | ||
186 | } | ||
187 | |||
188 | if (i == WAIT_STATUS_CLEAR_LOOP_COUNT) | ||
189 | dev_err(dev->dev, | ||
190 | "%s, can't clear the status bits in pipe_stat_reg, its value = 0x%x.\n", | ||
191 | __func__, PSB_RVDC32(pipe_stat_reg)); | ||
192 | |||
193 | if (pipe_stat_val & PIPE_VBLANK_STATUS) | ||
194 | mid_vblank_handler(dev, pipe); | ||
195 | |||
196 | if (pipe_stat_val & PIPE_TE_STATUS) | ||
197 | drm_handle_vblank(dev, pipe); | ||
198 | } | ||
199 | |||
200 | /* | ||
201 | * Display controller interrupt handler. | ||
202 | */ | ||
203 | static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat) | ||
204 | { | ||
205 | if (vdc_stat & _PSB_PIPEA_EVENT_FLAG) | ||
206 | mid_pipe_event_handler(dev, 0); | ||
207 | } | ||
208 | |||
209 | irqreturn_t psb_irq_handler(DRM_IRQ_ARGS) | ||
210 | { | ||
211 | struct drm_device *dev = (struct drm_device *) arg; | ||
212 | struct drm_psb_private *dev_priv = | ||
213 | (struct drm_psb_private *) dev->dev_private; | ||
214 | |||
215 | uint32_t vdc_stat, dsp_int = 0, sgx_int = 0; | ||
216 | int handled = 0; | ||
217 | |||
218 | spin_lock(&dev_priv->irqmask_lock); | ||
219 | |||
220 | vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R); | ||
221 | |||
222 | if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG) | ||
223 | dsp_int = 1; | ||
224 | |||
225 | if (vdc_stat & _PSB_IRQ_SGX_FLAG) | ||
226 | sgx_int = 1; | ||
227 | |||
228 | vdc_stat &= dev_priv->vdc_irq_mask; | ||
229 | spin_unlock(&dev_priv->irqmask_lock); | ||
230 | |||
231 | if (dsp_int && gma_power_is_on(dev)) { | ||
232 | psb_vdc_interrupt(dev, vdc_stat); | ||
233 | handled = 1; | ||
234 | } | ||
235 | |||
236 | if (sgx_int) { | ||
237 | /* Not expected - we have it masked, shut it up */ | ||
238 | u32 s, s2; | ||
239 | s = PSB_RSGX32(PSB_CR_EVENT_STATUS); | ||
240 | s2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2); | ||
241 | PSB_WSGX32(s, PSB_CR_EVENT_HOST_CLEAR); | ||
242 | PSB_WSGX32(s2, PSB_CR_EVENT_HOST_CLEAR2); | ||
243 | /* if s & _PSB_CE_TWOD_COMPLETE we have 2D done but | ||
244 | we may as well poll even if we add that ! */ | ||
245 | handled = 1; | ||
246 | } | ||
247 | |||
248 | PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R); | ||
249 | (void) PSB_RVDC32(PSB_INT_IDENTITY_R); | ||
250 | DRM_READMEMORYBARRIER(); | ||
251 | |||
252 | if (!handled) | ||
253 | return IRQ_NONE; | ||
254 | |||
255 | return IRQ_HANDLED; | ||
256 | } | ||
257 | |||
258 | void psb_irq_preinstall(struct drm_device *dev) | ||
259 | { | ||
260 | struct drm_psb_private *dev_priv = | ||
261 | (struct drm_psb_private *) dev->dev_private; | ||
262 | unsigned long irqflags; | ||
263 | |||
264 | spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); | ||
265 | |||
266 | if (gma_power_is_on(dev)) | ||
267 | PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); | ||
268 | if (dev->vblank_enabled[0]) | ||
269 | dev_priv->vdc_irq_mask |= _PSB_PIPEA_EVENT_FLAG; | ||
270 | if (dev->vblank_enabled[1]) | ||
271 | dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG; | ||
272 | if (dev->vblank_enabled[2]) | ||
273 | dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG; | ||
274 | |||
275 | /*This register is safe even if display island is off*/ | ||
276 | PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); | ||
277 | spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); | ||
278 | } | ||
279 | |||
280 | int psb_irq_postinstall(struct drm_device *dev) | ||
281 | { | ||
282 | struct drm_psb_private *dev_priv = | ||
283 | (struct drm_psb_private *) dev->dev_private; | ||
284 | unsigned long irqflags; | ||
285 | |||
286 | spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); | ||
287 | |||
288 | /* This register is safe even if display island is off */ | ||
289 | PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); | ||
290 | PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); | ||
291 | |||
292 | if (dev->vblank_enabled[0]) | ||
293 | psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE); | ||
294 | else | ||
295 | psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE); | ||
296 | |||
297 | if (dev->vblank_enabled[1]) | ||
298 | psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE); | ||
299 | else | ||
300 | psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE); | ||
301 | |||
302 | if (dev->vblank_enabled[2]) | ||
303 | psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE); | ||
304 | else | ||
305 | psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE); | ||
306 | |||
307 | spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); | ||
308 | return 0; | ||
309 | } | ||
310 | |||
311 | void psb_irq_uninstall(struct drm_device *dev) | ||
312 | { | ||
313 | struct drm_psb_private *dev_priv = | ||
314 | (struct drm_psb_private *) dev->dev_private; | ||
315 | unsigned long irqflags; | ||
316 | |||
317 | spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); | ||
318 | |||
319 | PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); | ||
320 | |||
321 | if (dev->vblank_enabled[0]) | ||
322 | psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE); | ||
323 | |||
324 | if (dev->vblank_enabled[1]) | ||
325 | psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE); | ||
326 | |||
327 | if (dev->vblank_enabled[2]) | ||
328 | psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE); | ||
329 | |||
330 | dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG | | ||
331 | _PSB_IRQ_MSVDX_FLAG | | ||
332 | _LNC_IRQ_TOPAZ_FLAG; | ||
333 | |||
334 | /* These two registers are safe even if display island is off */ | ||
335 | PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R); | ||
336 | PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R); | ||
337 | |||
338 | wmb(); | ||
339 | |||
340 | /* This register is safe even if display island is off */ | ||
341 | PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R); | ||
342 | spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); | ||
343 | } | ||
344 | |||
345 | void psb_irq_turn_on_dpst(struct drm_device *dev) | ||
346 | { | ||
347 | struct drm_psb_private *dev_priv = | ||
348 | (struct drm_psb_private *) dev->dev_private; | ||
349 | u32 hist_reg; | ||
350 | u32 pwm_reg; | ||
351 | |||
352 | if (gma_power_begin(dev, false)) { | ||
353 | PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL); | ||
354 | hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL); | ||
355 | PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL); | ||
356 | hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL); | ||
357 | |||
358 | PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC); | ||
359 | pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); | ||
360 | PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE | ||
361 | | PWM_PHASEIN_INT_ENABLE, | ||
362 | PWM_CONTROL_LOGIC); | ||
363 | pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); | ||
364 | |||
365 | psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE); | ||
366 | |||
367 | hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL); | ||
368 | PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR, | ||
369 | HISTOGRAM_INT_CONTROL); | ||
370 | pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); | ||
371 | PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE, | ||
372 | PWM_CONTROL_LOGIC); | ||
373 | |||
374 | gma_power_end(dev); | ||
375 | } | ||
376 | } | ||
377 | |||
378 | int psb_irq_enable_dpst(struct drm_device *dev) | ||
379 | { | ||
380 | struct drm_psb_private *dev_priv = | ||
381 | (struct drm_psb_private *) dev->dev_private; | ||
382 | unsigned long irqflags; | ||
383 | |||
384 | spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); | ||
385 | |||
386 | /* enable DPST */ | ||
387 | mid_enable_pipe_event(dev_priv, 0); | ||
388 | psb_irq_turn_on_dpst(dev); | ||
389 | |||
390 | spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); | ||
391 | return 0; | ||
392 | } | ||
393 | |||
394 | void psb_irq_turn_off_dpst(struct drm_device *dev) | ||
395 | { | ||
396 | struct drm_psb_private *dev_priv = | ||
397 | (struct drm_psb_private *) dev->dev_private; | ||
398 | u32 hist_reg; | ||
399 | u32 pwm_reg; | ||
400 | |||
401 | if (gma_power_begin(dev, false)) { | ||
402 | PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL); | ||
403 | hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL); | ||
404 | |||
405 | psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE); | ||
406 | |||
407 | pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); | ||
408 | PSB_WVDC32(pwm_reg & !(PWM_PHASEIN_INT_ENABLE), | ||
409 | PWM_CONTROL_LOGIC); | ||
410 | pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC); | ||
411 | |||
412 | gma_power_end(dev); | ||
413 | } | ||
414 | } | ||
415 | |||
416 | int psb_irq_disable_dpst(struct drm_device *dev) | ||
417 | { | ||
418 | struct drm_psb_private *dev_priv = | ||
419 | (struct drm_psb_private *) dev->dev_private; | ||
420 | unsigned long irqflags; | ||
421 | |||
422 | spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); | ||
423 | |||
424 | mid_disable_pipe_event(dev_priv, 0); | ||
425 | psb_irq_turn_off_dpst(dev); | ||
426 | |||
427 | spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); | ||
428 | |||
429 | return 0; | ||
430 | } | ||
431 | |||
432 | #ifdef PSB_FIXME | ||
433 | static int psb_vblank_do_wait(struct drm_device *dev, | ||
434 | unsigned int *sequence, atomic_t *counter) | ||
435 | { | ||
436 | unsigned int cur_vblank; | ||
437 | int ret = 0; | ||
438 | DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ, | ||
439 | (((cur_vblank = atomic_read(counter)) | ||
440 | - *sequence) <= (1 << 23))); | ||
441 | *sequence = cur_vblank; | ||
442 | |||
443 | return ret; | ||
444 | } | ||
445 | #endif | ||
446 | |||
447 | /* | ||
448 | * It is used to enable VBLANK interrupt | ||
449 | */ | ||
450 | int psb_enable_vblank(struct drm_device *dev, int pipe) | ||
451 | { | ||
452 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
453 | unsigned long irqflags; | ||
454 | uint32_t reg_val = 0; | ||
455 | uint32_t pipeconf_reg = mid_pipeconf(pipe); | ||
456 | |||
457 | if (gma_power_begin(dev, false)) { | ||
458 | reg_val = REG_READ(pipeconf_reg); | ||
459 | gma_power_end(dev); | ||
460 | } | ||
461 | |||
462 | if (!(reg_val & PIPEACONF_ENABLE)) | ||
463 | return -EINVAL; | ||
464 | |||
465 | spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); | ||
466 | |||
467 | mid_enable_pipe_event(dev_priv, pipe); | ||
468 | psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE); | ||
469 | |||
470 | spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); | ||
471 | |||
472 | return 0; | ||
473 | } | ||
474 | |||
475 | /* | ||
476 | * It is used to disable VBLANK interrupt | ||
477 | */ | ||
478 | void psb_disable_vblank(struct drm_device *dev, int pipe) | ||
479 | { | ||
480 | struct drm_psb_private *dev_priv = dev->dev_private; | ||
481 | unsigned long irqflags; | ||
482 | |||
483 | spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); | ||
484 | |||
485 | mid_disable_pipe_event(dev_priv, pipe); | ||
486 | psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE); | ||
487 | |||
488 | spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); | ||
489 | } | ||
490 | |||
491 | /* Called from drm generic code, passed a 'crtc', which | ||
492 | * we use as a pipe index | ||
493 | */ | ||
494 | u32 psb_get_vblank_counter(struct drm_device *dev, int pipe) | ||
495 | { | ||
496 | uint32_t high_frame = PIPEAFRAMEHIGH; | ||
497 | uint32_t low_frame = PIPEAFRAMEPIXEL; | ||
498 | uint32_t pipeconf_reg = PIPEACONF; | ||
499 | uint32_t reg_val = 0; | ||
500 | uint32_t high1 = 0, high2 = 0, low = 0, count = 0; | ||
501 | |||
502 | switch (pipe) { | ||
503 | case 0: | ||
504 | break; | ||
505 | case 1: | ||
506 | high_frame = PIPEBFRAMEHIGH; | ||
507 | low_frame = PIPEBFRAMEPIXEL; | ||
508 | pipeconf_reg = PIPEBCONF; | ||
509 | break; | ||
510 | case 2: | ||
511 | high_frame = PIPECFRAMEHIGH; | ||
512 | low_frame = PIPECFRAMEPIXEL; | ||
513 | pipeconf_reg = PIPECCONF; | ||
514 | break; | ||
515 | default: | ||
516 | dev_err(dev->dev, "%s, invalid pipe.\n", __func__); | ||
517 | return 0; | ||
518 | } | ||
519 | |||
520 | if (!gma_power_begin(dev, false)) | ||
521 | return 0; | ||
522 | |||
523 | reg_val = REG_READ(pipeconf_reg); | ||
524 | |||
525 | if (!(reg_val & PIPEACONF_ENABLE)) { | ||
526 | dev_err(dev->dev, "trying to get vblank count for disabled pipe %d\n", | ||
527 | pipe); | ||
528 | goto psb_get_vblank_counter_exit; | ||
529 | } | ||
530 | |||
531 | /* | ||
532 | * High & low register fields aren't synchronized, so make sure | ||
533 | * we get a low value that's stable across two reads of the high | ||
534 | * register. | ||
535 | */ | ||
536 | do { | ||
537 | high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | ||
538 | PIPE_FRAME_HIGH_SHIFT); | ||
539 | low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> | ||
540 | PIPE_FRAME_LOW_SHIFT); | ||
541 | high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | ||
542 | PIPE_FRAME_HIGH_SHIFT); | ||
543 | } while (high1 != high2); | ||
544 | |||
545 | count = (high1 << 8) | low; | ||
546 | |||
547 | psb_get_vblank_counter_exit: | ||
548 | |||
549 | gma_power_end(dev); | ||
550 | |||
551 | return count; | ||
552 | } | ||
553 | |||