drm/exynos: sending AVI and AUI info frames

This patch adds code for composing AVI and AUI info frames
and send them every VSYNC.

This patch is important for hdmi certification.

v3:
- Moved enums, macros to exynos_hdmi.c.
- Corrected hex format.
- Added static to hdmi_reg_infoframe.

v2:
- Added few blank lines.
- Corrected comments format.
- Added comments for 2's Complement calculation for check sum.

v1:
- Remove un-necessary blank lines.
- Change the case of hex constants.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Fahad Kunnathadi <fahad.k@samsung.com>
Signed-off-by: Shirish S <s.shirish@samsung.com>
Acked-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

1 files changed, 15 insertions, 2 deletions

diff --git a/drivers/gpu/drm/exynos/regs-hdmi.h b/drivers/gpu/drm/exynos/regs-hdmi.h
index 9cc7c5e9718c..970cdb518eb1 100644
--- a/drivers/gpu/drm/exynos/regs-hdmi.h
+++ b/drivers/gpu/drm/exynos/regs-hdmi.h
@@ -298,14 +298,14 @@
 #define HDMI_AVI_HEADER1                HDMI_CORE_BASE(0x0714)
 #define HDMI_AVI_HEADER2                HDMI_CORE_BASE(0x0718)
 #define HDMI_AVI_CHECK_SUM              HDMI_CORE_BASE(0x071C)
-#define HDMI_AVI_BYTE(n)                HDMI_CORE_BASE(0x0720 + 4 * (n))
+#define HDMI_AVI_BYTE(n)                HDMI_CORE_BASE(0x0720 + 4 * (n-1))
 
 #define HDMI_AUI_CON                    HDMI_CORE_BASE(0x0800)
 #define HDMI_AUI_HEADER0                HDMI_CORE_BASE(0x0810)
 #define HDMI_AUI_HEADER1                HDMI_CORE_BASE(0x0814)
 #define HDMI_AUI_HEADER2                HDMI_CORE_BASE(0x0818)
 #define HDMI_AUI_CHECK_SUM              HDMI_CORE_BASE(0x081C)
-#define HDMI_AUI_BYTE(n)                HDMI_CORE_BASE(0x0820 + 4 * (n))
+#define HDMI_AUI_BYTE(n)                HDMI_CORE_BASE(0x0820 + 4 * (n-1))
 
 #define HDMI_MPG_CON                    HDMI_CORE_BASE(0x0900)
 #define HDMI_MPG_CHECK_SUM              HDMI_CORE_BASE(0x091C)
@@ -338,6 +338,19 @@
 #define HDMI_AN_SEED_2                  HDMI_CORE_BASE(0x0E60)
 #define HDMI_AN_SEED_3                  HDMI_CORE_BASE(0x0E64)
 
+/* AVI bit definition */
+#define HDMI_AVI_CON_DO_NOT_TRANSMIT    (0 << 1)
+#define HDMI_AVI_CON_EVERY_VSYNC        (1 << 1)
+
+#define AVI_ACTIVE_FORMAT_VALID (1 << 4)
+#define AVI_UNDERSCANNED_DISPLAY_VALID  (1 << 1)
+
+/* AUI bit definition */
+#define HDMI_AUI_CON_NO_TRAN            (0 << 0)
+
+/* VSI bit definition */
+#define HDMI_VSI_CON_DO_NOT_TRANSMIT    (0 << 0)
+
 /* HDCP related registers */
 #define HDMI_HDCP_SHA1(n)               HDMI_CORE_BASE(0x7000 + 4 * (n))
 #define HDMI_HDCP_KSV_LIST(n)           HDMI_CORE_BASE(0x7050 + 4 * (n))