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authorImre Deak <imre.deak@intel.com>2013-03-26 09:14:18 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-03-27 12:13:44 -0400
commit2db76d7c3c6db93058f983c8240f7c7c25e87ee6 (patch)
treea35f01706b353841b71645da050bc721c9f0467b /drivers/gpu/drm/drm_cache.c
parent693db1842d864ca2771e881127cdb4d09979758b (diff)
lib/scatterlist: sg_page_iter: support sg lists w/o backing pages
The i915 driver uses sg lists for memory without backing 'struct page' pages, similarly to other IO memory regions, setting only the DMA address for these. It does this, so that it can program the HW MMU tables in a uniform way both for sg lists with and without backing pages. Without a valid page pointer we can't call nth_page to get the current page in __sg_page_iter_next, so add a helper that relevant users can call separately. Also add a helper to get the DMA address of the current page (idea from Daniel). Convert all places in i915, to use the new API. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/drm_cache.c')
-rw-r--r--drivers/gpu/drm/drm_cache.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index bc8edbeca3fd..bb8f58012189 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -109,7 +109,7 @@ drm_clflush_sg(struct sg_table *st)
109 109
110 mb(); 110 mb();
111 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) 111 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
112 drm_clflush_page(sg_iter.page); 112 drm_clflush_page(sg_page_iter_page(&sg_iter));
113 mb(); 113 mb();
114 114
115 return; 115 return;