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authorGrant Likely <grant.likely@secretlab.ca>2012-05-08 13:35:37 -0400
committerGrant Likely <grant.likely@secretlab.ca>2012-05-08 13:35:37 -0400
commit7b96c686223a5c902d6a59c7d178f3904f0ab757 (patch)
treefe328ed56ad3719de3cfebad72ef74e34f1ed92b /drivers/gpio
parentf141ed65f256ec036c7fba604da6b7c448096ef9 (diff)
parentd48b97b403d23f6df0b990cee652bdf9a52337a3 (diff)
Merge tag 'v3.4-rc6' into gpio/next
Linux 3.4-rc6
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/Kconfig2
-rw-r--r--drivers/gpio/gpio-adp5588.c2
-rw-r--r--drivers/gpio/gpio-pxa.c21
-rw-r--r--drivers/gpio/gpio-samsung.c16
-rw-r--r--drivers/gpio/gpio-sodaville.c23
-rw-r--r--drivers/gpio/gpio-tegra.c59
-rw-r--r--drivers/gpio/gpiolib-of.c2
7 files changed, 84 insertions, 41 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 1042c3f534f4..7875c3f93662 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -435,7 +435,7 @@ config GPIO_ML_IOH
435 435
436config GPIO_SODAVILLE 436config GPIO_SODAVILLE
437 bool "Intel Sodaville GPIO support" 437 bool "Intel Sodaville GPIO support"
438 depends on X86 && PCI && OF && BROKEN 438 depends on X86 && PCI && OF
439 select GPIO_GENERIC 439 select GPIO_GENERIC
440 select GENERIC_IRQ_CHIP 440 select GENERIC_IRQ_CHIP
441 help 441 help
diff --git a/drivers/gpio/gpio-adp5588.c b/drivers/gpio/gpio-adp5588.c
index 9ad1703d1408..ae5d7f12ce66 100644
--- a/drivers/gpio/gpio-adp5588.c
+++ b/drivers/gpio/gpio-adp5588.c
@@ -252,7 +252,7 @@ static irqreturn_t adp5588_irq_handler(int irq, void *devid)
252 if (ret < 0) 252 if (ret < 0)
253 memset(dev->irq_stat, 0, ARRAY_SIZE(dev->irq_stat)); 253 memset(dev->irq_stat, 0, ARRAY_SIZE(dev->irq_stat));
254 254
255 for (bank = 0; bank <= ADP5588_BANK(ADP5588_MAXGPIO); 255 for (bank = 0, bit = 0; bank <= ADP5588_BANK(ADP5588_MAXGPIO);
256 bank++, bit = 0) { 256 bank++, bit = 0) {
257 pending = dev->irq_stat[bank] & dev->irq_mask[bank]; 257 pending = dev->irq_stat[bank] & dev->irq_mask[bank];
258 258
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 5689ce62fd81..fc3ace3fd4cb 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -64,6 +64,7 @@ struct pxa_gpio_chip {
64 unsigned long irq_mask; 64 unsigned long irq_mask;
65 unsigned long irq_edge_rise; 65 unsigned long irq_edge_rise;
66 unsigned long irq_edge_fall; 66 unsigned long irq_edge_fall;
67 int (*set_wake)(unsigned int gpio, unsigned int on);
67 68
68#ifdef CONFIG_PM 69#ifdef CONFIG_PM
69 unsigned long saved_gplr; 70 unsigned long saved_gplr;
@@ -269,7 +270,8 @@ static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
269 (value ? GPSR_OFFSET : GPCR_OFFSET)); 270 (value ? GPSR_OFFSET : GPCR_OFFSET));
270} 271}
271 272
272static int __devinit pxa_init_gpio_chip(int gpio_end) 273static int __devinit pxa_init_gpio_chip(int gpio_end,
274 int (*set_wake)(unsigned int, unsigned int))
273{ 275{
274 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; 276 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
275 struct pxa_gpio_chip *chips; 277 struct pxa_gpio_chip *chips;
@@ -285,6 +287,7 @@ static int __devinit pxa_init_gpio_chip(int gpio_end)
285 287
286 sprintf(chips[i].label, "gpio-%d", i); 288 sprintf(chips[i].label, "gpio-%d", i);
287 chips[i].regbase = gpio_reg_base + BANK_OFF(i); 289 chips[i].regbase = gpio_reg_base + BANK_OFF(i);
290 chips[i].set_wake = set_wake;
288 291
289 c->base = gpio; 292 c->base = gpio;
290 c->label = chips[i].label; 293 c->label = chips[i].label;
@@ -412,6 +415,17 @@ static void pxa_mask_muxed_gpio(struct irq_data *d)
412 writel_relaxed(gfer, c->regbase + GFER_OFFSET); 415 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
413} 416}
414 417
418static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
419{
420 int gpio = pxa_irq_to_gpio(d->irq);
421 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
422
423 if (c->set_wake)
424 return c->set_wake(gpio, on);
425 else
426 return 0;
427}
428
415static void pxa_unmask_muxed_gpio(struct irq_data *d) 429static void pxa_unmask_muxed_gpio(struct irq_data *d)
416{ 430{
417 int gpio = pxa_irq_to_gpio(d->irq); 431 int gpio = pxa_irq_to_gpio(d->irq);
@@ -427,6 +441,7 @@ static struct irq_chip pxa_muxed_gpio_chip = {
427 .irq_mask = pxa_mask_muxed_gpio, 441 .irq_mask = pxa_mask_muxed_gpio,
428 .irq_unmask = pxa_unmask_muxed_gpio, 442 .irq_unmask = pxa_unmask_muxed_gpio,
429 .irq_set_type = pxa_gpio_irq_type, 443 .irq_set_type = pxa_gpio_irq_type,
444 .irq_set_wake = pxa_gpio_set_wake,
430}; 445};
431 446
432static int pxa_gpio_nums(void) 447static int pxa_gpio_nums(void)
@@ -471,6 +486,7 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
471 struct pxa_gpio_chip *c; 486 struct pxa_gpio_chip *c;
472 struct resource *res; 487 struct resource *res;
473 struct clk *clk; 488 struct clk *clk;
489 struct pxa_gpio_platform_data *info;
474 int gpio, irq, ret; 490 int gpio, irq, ret;
475 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; 491 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
476 492
@@ -516,7 +532,8 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
516 } 532 }
517 533
518 /* Initialize GPIO chips */ 534 /* Initialize GPIO chips */
519 pxa_init_gpio_chip(pxa_last_gpio); 535 info = dev_get_platdata(&pdev->dev);
536 pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL);
520 537
521 /* clear all GPIO edge detects */ 538 /* clear all GPIO edge detects */
522 for_each_gpio_chip(gpio, c) { 539 for_each_gpio_chip(gpio, c) {
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 46277877b7ec..19d6fc0229c3 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2382,8 +2382,8 @@ static struct samsung_gpio_chip exynos4_gpios_3[] = {
2382#endif 2382#endif
2383}; 2383};
2384 2384
2385static struct samsung_gpio_chip exynos5_gpios_1[] = {
2386#ifdef CONFIG_ARCH_EXYNOS5 2385#ifdef CONFIG_ARCH_EXYNOS5
2386static struct samsung_gpio_chip exynos5_gpios_1[] = {
2387 { 2387 {
2388 .chip = { 2388 .chip = {
2389 .base = EXYNOS5_GPA0(0), 2389 .base = EXYNOS5_GPA0(0),
@@ -2541,11 +2541,11 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
2541 .to_irq = samsung_gpiolib_to_irq, 2541 .to_irq = samsung_gpiolib_to_irq,
2542 }, 2542 },
2543 }, 2543 },
2544#endif
2545}; 2544};
2545#endif
2546 2546
2547static struct samsung_gpio_chip exynos5_gpios_2[] = {
2548#ifdef CONFIG_ARCH_EXYNOS5 2547#ifdef CONFIG_ARCH_EXYNOS5
2548static struct samsung_gpio_chip exynos5_gpios_2[] = {
2549 { 2549 {
2550 .chip = { 2550 .chip = {
2551 .base = EXYNOS5_GPE0(0), 2551 .base = EXYNOS5_GPE0(0),
@@ -2602,11 +2602,11 @@ static struct samsung_gpio_chip exynos5_gpios_2[] = {
2602 2602
2603 }, 2603 },
2604 }, 2604 },
2605#endif
2606}; 2605};
2606#endif
2607 2607
2608static struct samsung_gpio_chip exynos5_gpios_3[] = {
2609#ifdef CONFIG_ARCH_EXYNOS5 2608#ifdef CONFIG_ARCH_EXYNOS5
2609static struct samsung_gpio_chip exynos5_gpios_3[] = {
2610 { 2610 {
2611 .chip = { 2611 .chip = {
2612 .base = EXYNOS5_GPV0(0), 2612 .base = EXYNOS5_GPV0(0),
@@ -2638,11 +2638,11 @@ static struct samsung_gpio_chip exynos5_gpios_3[] = {
2638 .label = "GPV4", 2638 .label = "GPV4",
2639 }, 2639 },
2640 }, 2640 },
2641#endif
2642}; 2641};
2642#endif
2643 2643
2644static struct samsung_gpio_chip exynos5_gpios_4[] = {
2645#ifdef CONFIG_ARCH_EXYNOS5 2644#ifdef CONFIG_ARCH_EXYNOS5
2645static struct samsung_gpio_chip exynos5_gpios_4[] = {
2646 { 2646 {
2647 .chip = { 2647 .chip = {
2648 .base = EXYNOS5_GPZ(0), 2648 .base = EXYNOS5_GPZ(0),
@@ -2650,8 +2650,8 @@ static struct samsung_gpio_chip exynos5_gpios_4[] = {
2650 .label = "GPZ", 2650 .label = "GPZ",
2651 }, 2651 },
2652 }, 2652 },
2653#endif
2654}; 2653};
2654#endif
2655 2655
2656 2656
2657#if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) 2657#if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
diff --git a/drivers/gpio/gpio-sodaville.c b/drivers/gpio/gpio-sodaville.c
index e20dc737dd4e..820209c420e3 100644
--- a/drivers/gpio/gpio-sodaville.c
+++ b/drivers/gpio/gpio-sodaville.c
@@ -41,7 +41,7 @@
41struct sdv_gpio_chip_data { 41struct sdv_gpio_chip_data {
42 int irq_base; 42 int irq_base;
43 void __iomem *gpio_pub_base; 43 void __iomem *gpio_pub_base;
44 struct irq_domain id; 44 struct irq_domain *id;
45 struct irq_chip_generic *gc; 45 struct irq_chip_generic *gc;
46 struct bgpio_chip bgpio; 46 struct bgpio_chip bgpio;
47}; 47};
@@ -51,10 +51,9 @@ static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
51 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 51 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
52 struct sdv_gpio_chip_data *sd = gc->private; 52 struct sdv_gpio_chip_data *sd = gc->private;
53 void __iomem *type_reg; 53 void __iomem *type_reg;
54 u32 irq_offs = d->irq - sd->irq_base;
55 u32 reg; 54 u32 reg;
56 55
57 if (irq_offs < 8) 56 if (d->hwirq < 8)
58 type_reg = sd->gpio_pub_base + GPIT1R0; 57 type_reg = sd->gpio_pub_base + GPIT1R0;
59 else 58 else
60 type_reg = sd->gpio_pub_base + GPIT1R1; 59 type_reg = sd->gpio_pub_base + GPIT1R1;
@@ -63,11 +62,11 @@ static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
63 62
64 switch (type) { 63 switch (type) {
65 case IRQ_TYPE_LEVEL_HIGH: 64 case IRQ_TYPE_LEVEL_HIGH:
66 reg &= ~BIT(4 * (irq_offs % 8)); 65 reg &= ~BIT(4 * (d->hwirq % 8));
67 break; 66 break;
68 67
69 case IRQ_TYPE_LEVEL_LOW: 68 case IRQ_TYPE_LEVEL_LOW:
70 reg |= BIT(4 * (irq_offs % 8)); 69 reg |= BIT(4 * (d->hwirq % 8));
71 break; 70 break;
72 71
73 default: 72 default:
@@ -91,7 +90,7 @@ static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
91 u32 irq_bit = __fls(irq_stat); 90 u32 irq_bit = __fls(irq_stat);
92 91
93 irq_stat &= ~BIT(irq_bit); 92 irq_stat &= ~BIT(irq_bit);
94 generic_handle_irq(sd->irq_base + irq_bit); 93 generic_handle_irq(irq_find_mapping(sd->id, irq_bit));
95 } 94 }
96 95
97 return IRQ_HANDLED; 96 return IRQ_HANDLED;
@@ -127,7 +126,7 @@ static int sdv_xlate(struct irq_domain *h, struct device_node *node,
127} 126}
128 127
129static struct irq_domain_ops irq_domain_sdv_ops = { 128static struct irq_domain_ops irq_domain_sdv_ops = {
130 .dt_translate = sdv_xlate, 129 .xlate = sdv_xlate,
131}; 130};
132 131
133static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd, 132static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
@@ -149,10 +148,6 @@ static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
149 if (ret) 148 if (ret)
150 goto out_free_desc; 149 goto out_free_desc;
151 150
152 sd->id.irq_base = sd->irq_base;
153 sd->id.of_node = of_node_get(pdev->dev.of_node);
154 sd->id.ops = &irq_domain_sdv_ops;
155
156 /* 151 /*
157 * This gpio irq controller latches level irqs. Testing shows that if 152 * This gpio irq controller latches level irqs. Testing shows that if
158 * we unmask & ACK the IRQ before the source of the interrupt is gone 153 * we unmask & ACK the IRQ before the source of the interrupt is gone
@@ -179,7 +174,10 @@ static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
179 IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 174 IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
180 IRQ_LEVEL | IRQ_NOPROBE); 175 IRQ_LEVEL | IRQ_NOPROBE);
181 176
182 irq_domain_add(&sd->id); 177 sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
178 sd->irq_base, 0, &irq_domain_sdv_ops, sd);
179 if (!sd->id)
180 goto out_free_irq;
183 return 0; 181 return 0;
184out_free_irq: 182out_free_irq:
185 free_irq(pdev->irq, sd); 183 free_irq(pdev->irq, sd);
@@ -260,7 +258,6 @@ static void sdv_gpio_remove(struct pci_dev *pdev)
260{ 258{
261 struct sdv_gpio_chip_data *sd = pci_get_drvdata(pdev); 259 struct sdv_gpio_chip_data *sd = pci_get_drvdata(pdev);
262 260
263 irq_domain_del(&sd->id);
264 free_irq(pdev->irq, sd); 261 free_irq(pdev->irq, sd);
265 irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS); 262 irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
266 263
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 32de6707e3c4..12f349b3830d 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -22,7 +22,7 @@
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/of.h> 25#include <linux/of_device.h>
26#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/irqdomain.h> 28#include <linux/irqdomain.h>
@@ -37,7 +37,8 @@
37#define GPIO_PORT(x) (((x) >> 3) & 0x3) 37#define GPIO_PORT(x) (((x) >> 3) & 0x3)
38#define GPIO_BIT(x) ((x) & 0x7) 38#define GPIO_BIT(x) ((x) & 0x7)
39 39
40#define GPIO_REG(x) (GPIO_BANK(x) * 0x80 + GPIO_PORT(x) * 4) 40#define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \
41 GPIO_PORT(x) * 4)
41 42
42#define GPIO_CNF(x) (GPIO_REG(x) + 0x00) 43#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
43#define GPIO_OE(x) (GPIO_REG(x) + 0x10) 44#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
@@ -48,12 +49,12 @@
48#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60) 49#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
49#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70) 50#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
50 51
51#define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800) 52#define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
52#define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810) 53#define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
53#define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820) 54#define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
54#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840) 55#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
55#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850) 56#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
56#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860) 57#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
57 58
58#define GPIO_INT_LVL_MASK 0x010101 59#define GPIO_INT_LVL_MASK 0x010101
59#define GPIO_INT_LVL_EDGE_RISING 0x000101 60#define GPIO_INT_LVL_EDGE_RISING 0x000101
@@ -78,6 +79,8 @@ struct tegra_gpio_bank {
78static struct irq_domain *irq_domain; 79static struct irq_domain *irq_domain;
79static void __iomem *regs; 80static void __iomem *regs;
80static u32 tegra_gpio_bank_count; 81static u32 tegra_gpio_bank_count;
82static u32 tegra_gpio_bank_stride;
83static u32 tegra_gpio_upper_offset;
81static struct tegra_gpio_bank *tegra_gpio_banks; 84static struct tegra_gpio_bank *tegra_gpio_banks;
82 85
83static inline void tegra_gpio_writel(u32 val, u32 reg) 86static inline void tegra_gpio_writel(u32 val, u32 reg)
@@ -333,6 +336,26 @@ static struct irq_chip tegra_gpio_irq_chip = {
333#endif 336#endif
334}; 337};
335 338
339struct tegra_gpio_soc_config {
340 u32 bank_stride;
341 u32 upper_offset;
342};
343
344static struct tegra_gpio_soc_config tegra20_gpio_config = {
345 .bank_stride = 0x80,
346 .upper_offset = 0x800,
347};
348
349static struct tegra_gpio_soc_config tegra30_gpio_config = {
350 .bank_stride = 0x100,
351 .upper_offset = 0x80,
352};
353
354static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
355 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
356 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
357 { },
358};
336 359
337/* This lock class tells lockdep that GPIO irqs are in a different 360/* This lock class tells lockdep that GPIO irqs are in a different
338 * category than their parents, so it won't report false recursion. 361 * category than their parents, so it won't report false recursion.
@@ -341,6 +364,8 @@ static struct lock_class_key gpio_lock_class;
341 364
342static int __devinit tegra_gpio_probe(struct platform_device *pdev) 365static int __devinit tegra_gpio_probe(struct platform_device *pdev)
343{ 366{
367 const struct of_device_id *match;
368 struct tegra_gpio_soc_config *config;
344 int irq_base; 369 int irq_base;
345 struct resource *res; 370 struct resource *res;
346 struct tegra_gpio_bank *bank; 371 struct tegra_gpio_bank *bank;
@@ -348,6 +373,15 @@ static int __devinit tegra_gpio_probe(struct platform_device *pdev)
348 int i; 373 int i;
349 int j; 374 int j;
350 375
376 match = of_match_device(tegra_gpio_of_match, &pdev->dev);
377 if (match)
378 config = (struct tegra_gpio_soc_config *)match->data;
379 else
380 config = &tegra20_gpio_config;
381
382 tegra_gpio_bank_stride = config->bank_stride;
383 tegra_gpio_upper_offset = config->upper_offset;
384
351 for (;;) { 385 for (;;) {
352 res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count); 386 res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
353 if (!res) 387 if (!res)
@@ -402,7 +436,7 @@ static int __devinit tegra_gpio_probe(struct platform_device *pdev)
402 return -ENODEV; 436 return -ENODEV;
403 } 437 }
404 438
405 for (i = 0; i < 7; i++) { 439 for (i = 0; i < tegra_gpio_bank_count; i++) {
406 for (j = 0; j < 4; j++) { 440 for (j = 0; j < 4; j++) {
407 int gpio = tegra_gpio_compose(i, j, 0); 441 int gpio = tegra_gpio_compose(i, j, 0);
408 tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio)); 442 tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
@@ -441,11 +475,6 @@ static int __devinit tegra_gpio_probe(struct platform_device *pdev)
441 return 0; 475 return 0;
442} 476}
443 477
444static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
445 { .compatible = "nvidia,tegra20-gpio", },
446 { },
447};
448
449static struct platform_driver tegra_gpio_driver = { 478static struct platform_driver tegra_gpio_driver = {
450 .driver = { 479 .driver = {
451 .name = "tegra-gpio", 480 .name = "tegra-gpio",
@@ -485,7 +514,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
485 int i; 514 int i;
486 int j; 515 int j;
487 516
488 for (i = 0; i < 7; i++) { 517 for (i = 0; i < tegra_gpio_bank_count; i++) {
489 for (j = 0; j < 4; j++) { 518 for (j = 0; j < 4; j++) {
490 int gpio = tegra_gpio_compose(i, j, 0); 519 int gpio = tegra_gpio_compose(i, j, 0);
491 seq_printf(s, 520 seq_printf(s,
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
index bba81216b4db..bf984b6dc477 100644
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -140,7 +140,7 @@ int of_gpio_simple_xlate(struct gpio_chip *gc,
140 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) 140 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
141 return -EINVAL; 141 return -EINVAL;
142 142
143 if (gpiospec->args[0] > gc->ngpio) 143 if (gpiospec->args[0] >= gc->ngpio)
144 return -EINVAL; 144 return -EINVAL;
145 145
146 if (flags) 146 if (flags)