diff options
author | Linus Walleij <linus.walleij@linaro.org> | 2015-01-20 05:03:07 -0500 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2015-01-20 05:03:07 -0500 |
commit | ee65ef609aa81539ac3792df88f04bfe29a77546 (patch) | |
tree | 6816eaa3d45fa1078408f2ccfa5f88d32733d1d9 /drivers/gpio | |
parent | 7a839e9a277d4a410a9b015d561ff09739bc0ff6 (diff) | |
parent | ec6f34e5b552fb0a52e6aae1a5afbbb1605cc6cc (diff) |
Merge tag 'v3.19-rc5' into devel
Linux 3.19-rc5
Diffstat (limited to 'drivers/gpio')
-rw-r--r-- | drivers/gpio/gpio-dln2.c | 156 | ||||
-rw-r--r-- | drivers/gpio/gpio-grgpio.c | 3 |
2 files changed, 69 insertions, 90 deletions
diff --git a/drivers/gpio/gpio-dln2.c b/drivers/gpio/gpio-dln2.c index 3e07232b8370..dbdb4de82c6d 100644 --- a/drivers/gpio/gpio-dln2.c +++ b/drivers/gpio/gpio-dln2.c | |||
@@ -47,13 +47,6 @@ | |||
47 | 47 | ||
48 | #define DLN2_GPIO_MAX_PINS 32 | 48 | #define DLN2_GPIO_MAX_PINS 32 |
49 | 49 | ||
50 | struct dln2_irq_work { | ||
51 | struct work_struct work; | ||
52 | struct dln2_gpio *dln2; | ||
53 | int pin; | ||
54 | int type; | ||
55 | }; | ||
56 | |||
57 | struct dln2_gpio { | 50 | struct dln2_gpio { |
58 | struct platform_device *pdev; | 51 | struct platform_device *pdev; |
59 | struct gpio_chip gpio; | 52 | struct gpio_chip gpio; |
@@ -64,10 +57,12 @@ struct dln2_gpio { | |||
64 | */ | 57 | */ |
65 | DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS); | 58 | DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS); |
66 | 59 | ||
67 | DECLARE_BITMAP(irqs_masked, DLN2_GPIO_MAX_PINS); | 60 | /* active IRQs - not synced to hardware */ |
68 | DECLARE_BITMAP(irqs_enabled, DLN2_GPIO_MAX_PINS); | 61 | DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS); |
69 | DECLARE_BITMAP(irqs_pending, DLN2_GPIO_MAX_PINS); | 62 | /* active IRQS - synced to hardware */ |
70 | struct dln2_irq_work *irq_work; | 63 | DECLARE_BITMAP(enabled_irqs, DLN2_GPIO_MAX_PINS); |
64 | int irq_type[DLN2_GPIO_MAX_PINS]; | ||
65 | struct mutex irq_lock; | ||
71 | }; | 66 | }; |
72 | 67 | ||
73 | struct dln2_gpio_pin { | 68 | struct dln2_gpio_pin { |
@@ -141,16 +136,16 @@ static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin) | |||
141 | return !!ret; | 136 | return !!ret; |
142 | } | 137 | } |
143 | 138 | ||
144 | static void dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2, | 139 | static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2, |
145 | unsigned int pin, int value) | 140 | unsigned int pin, int value) |
146 | { | 141 | { |
147 | struct dln2_gpio_pin_val req = { | 142 | struct dln2_gpio_pin_val req = { |
148 | .pin = cpu_to_le16(pin), | 143 | .pin = cpu_to_le16(pin), |
149 | .value = value, | 144 | .value = value, |
150 | }; | 145 | }; |
151 | 146 | ||
152 | dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req, | 147 | return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req, |
153 | sizeof(req)); | 148 | sizeof(req)); |
154 | } | 149 | } |
155 | 150 | ||
156 | #define DLN2_GPIO_DIRECTION_IN 0 | 151 | #define DLN2_GPIO_DIRECTION_IN 0 |
@@ -267,6 +262,13 @@ static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |||
267 | static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | 262 | static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
268 | int value) | 263 | int value) |
269 | { | 264 | { |
265 | struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio); | ||
266 | int ret; | ||
267 | |||
268 | ret = dln2_gpio_pin_set_out_val(dln2, offset, value); | ||
269 | if (ret < 0) | ||
270 | return ret; | ||
271 | |||
270 | return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT); | 272 | return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT); |
271 | } | 273 | } |
272 | 274 | ||
@@ -297,36 +299,13 @@ static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin, | |||
297 | &req, sizeof(req)); | 299 | &req, sizeof(req)); |
298 | } | 300 | } |
299 | 301 | ||
300 | static void dln2_irq_work(struct work_struct *w) | 302 | static void dln2_irq_unmask(struct irq_data *irqd) |
301 | { | ||
302 | struct dln2_irq_work *iw = container_of(w, struct dln2_irq_work, work); | ||
303 | struct dln2_gpio *dln2 = iw->dln2; | ||
304 | u8 type = iw->type & DLN2_GPIO_EVENT_MASK; | ||
305 | |||
306 | if (test_bit(iw->pin, dln2->irqs_enabled)) | ||
307 | dln2_gpio_set_event_cfg(dln2, iw->pin, type, 0); | ||
308 | else | ||
309 | dln2_gpio_set_event_cfg(dln2, iw->pin, DLN2_GPIO_EVENT_NONE, 0); | ||
310 | } | ||
311 | |||
312 | static void dln2_irq_enable(struct irq_data *irqd) | ||
313 | { | ||
314 | struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); | ||
315 | struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio); | ||
316 | int pin = irqd_to_hwirq(irqd); | ||
317 | |||
318 | set_bit(pin, dln2->irqs_enabled); | ||
319 | schedule_work(&dln2->irq_work[pin].work); | ||
320 | } | ||
321 | |||
322 | static void dln2_irq_disable(struct irq_data *irqd) | ||
323 | { | 303 | { |
324 | struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); | 304 | struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); |
325 | struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio); | 305 | struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio); |
326 | int pin = irqd_to_hwirq(irqd); | 306 | int pin = irqd_to_hwirq(irqd); |
327 | 307 | ||
328 | clear_bit(pin, dln2->irqs_enabled); | 308 | set_bit(pin, dln2->unmasked_irqs); |
329 | schedule_work(&dln2->irq_work[pin].work); | ||
330 | } | 309 | } |
331 | 310 | ||
332 | static void dln2_irq_mask(struct irq_data *irqd) | 311 | static void dln2_irq_mask(struct irq_data *irqd) |
@@ -335,27 +314,7 @@ static void dln2_irq_mask(struct irq_data *irqd) | |||
335 | struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio); | 314 | struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio); |
336 | int pin = irqd_to_hwirq(irqd); | 315 | int pin = irqd_to_hwirq(irqd); |
337 | 316 | ||
338 | set_bit(pin, dln2->irqs_masked); | 317 | clear_bit(pin, dln2->unmasked_irqs); |
339 | } | ||
340 | |||
341 | static void dln2_irq_unmask(struct irq_data *irqd) | ||
342 | { | ||
343 | struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); | ||
344 | struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio); | ||
345 | struct device *dev = dln2->gpio.dev; | ||
346 | int pin = irqd_to_hwirq(irqd); | ||
347 | |||
348 | if (test_and_clear_bit(pin, dln2->irqs_pending)) { | ||
349 | int irq; | ||
350 | |||
351 | irq = irq_find_mapping(dln2->gpio.irqdomain, pin); | ||
352 | if (!irq) { | ||
353 | dev_err(dev, "pin %d not mapped to IRQ\n", pin); | ||
354 | return; | ||
355 | } | ||
356 | |||
357 | generic_handle_irq(irq); | ||
358 | } | ||
359 | } | 318 | } |
360 | 319 | ||
361 | static int dln2_irq_set_type(struct irq_data *irqd, unsigned type) | 320 | static int dln2_irq_set_type(struct irq_data *irqd, unsigned type) |
@@ -366,19 +325,19 @@ static int dln2_irq_set_type(struct irq_data *irqd, unsigned type) | |||
366 | 325 | ||
367 | switch (type) { | 326 | switch (type) { |
368 | case IRQ_TYPE_LEVEL_HIGH: | 327 | case IRQ_TYPE_LEVEL_HIGH: |
369 | dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_HIGH; | 328 | dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_HIGH; |
370 | break; | 329 | break; |
371 | case IRQ_TYPE_LEVEL_LOW: | 330 | case IRQ_TYPE_LEVEL_LOW: |
372 | dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_LOW; | 331 | dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_LOW; |
373 | break; | 332 | break; |
374 | case IRQ_TYPE_EDGE_BOTH: | 333 | case IRQ_TYPE_EDGE_BOTH: |
375 | dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE; | 334 | dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE; |
376 | break; | 335 | break; |
377 | case IRQ_TYPE_EDGE_RISING: | 336 | case IRQ_TYPE_EDGE_RISING: |
378 | dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_RISING; | 337 | dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_RISING; |
379 | break; | 338 | break; |
380 | case IRQ_TYPE_EDGE_FALLING: | 339 | case IRQ_TYPE_EDGE_FALLING: |
381 | dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_FALLING; | 340 | dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_FALLING; |
382 | break; | 341 | break; |
383 | default: | 342 | default: |
384 | return -EINVAL; | 343 | return -EINVAL; |
@@ -387,13 +346,50 @@ static int dln2_irq_set_type(struct irq_data *irqd, unsigned type) | |||
387 | return 0; | 346 | return 0; |
388 | } | 347 | } |
389 | 348 | ||
349 | static void dln2_irq_bus_lock(struct irq_data *irqd) | ||
350 | { | ||
351 | struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); | ||
352 | struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio); | ||
353 | |||
354 | mutex_lock(&dln2->irq_lock); | ||
355 | } | ||
356 | |||
357 | static void dln2_irq_bus_unlock(struct irq_data *irqd) | ||
358 | { | ||
359 | struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); | ||
360 | struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio); | ||
361 | int pin = irqd_to_hwirq(irqd); | ||
362 | int enabled, unmasked; | ||
363 | unsigned type; | ||
364 | int ret; | ||
365 | |||
366 | enabled = test_bit(pin, dln2->enabled_irqs); | ||
367 | unmasked = test_bit(pin, dln2->unmasked_irqs); | ||
368 | |||
369 | if (enabled != unmasked) { | ||
370 | if (unmasked) { | ||
371 | type = dln2->irq_type[pin] & DLN2_GPIO_EVENT_MASK; | ||
372 | set_bit(pin, dln2->enabled_irqs); | ||
373 | } else { | ||
374 | type = DLN2_GPIO_EVENT_NONE; | ||
375 | clear_bit(pin, dln2->enabled_irqs); | ||
376 | } | ||
377 | |||
378 | ret = dln2_gpio_set_event_cfg(dln2, pin, type, 0); | ||
379 | if (ret) | ||
380 | dev_err(dln2->gpio.dev, "failed to set event\n"); | ||
381 | } | ||
382 | |||
383 | mutex_unlock(&dln2->irq_lock); | ||
384 | } | ||
385 | |||
390 | static struct irq_chip dln2_gpio_irqchip = { | 386 | static struct irq_chip dln2_gpio_irqchip = { |
391 | .name = "dln2-irq", | 387 | .name = "dln2-irq", |
392 | .irq_enable = dln2_irq_enable, | ||
393 | .irq_disable = dln2_irq_disable, | ||
394 | .irq_mask = dln2_irq_mask, | 388 | .irq_mask = dln2_irq_mask, |
395 | .irq_unmask = dln2_irq_unmask, | 389 | .irq_unmask = dln2_irq_unmask, |
396 | .irq_set_type = dln2_irq_set_type, | 390 | .irq_set_type = dln2_irq_set_type, |
391 | .irq_bus_lock = dln2_irq_bus_lock, | ||
392 | .irq_bus_sync_unlock = dln2_irq_bus_unlock, | ||
397 | }; | 393 | }; |
398 | 394 | ||
399 | static void dln2_gpio_event(struct platform_device *pdev, u16 echo, | 395 | static void dln2_gpio_event(struct platform_device *pdev, u16 echo, |
@@ -426,14 +422,7 @@ static void dln2_gpio_event(struct platform_device *pdev, u16 echo, | |||
426 | return; | 422 | return; |
427 | } | 423 | } |
428 | 424 | ||
429 | if (!test_bit(pin, dln2->irqs_enabled)) | 425 | switch (dln2->irq_type[pin]) { |
430 | return; | ||
431 | if (test_bit(pin, dln2->irqs_masked)) { | ||
432 | set_bit(pin, dln2->irqs_pending); | ||
433 | return; | ||
434 | } | ||
435 | |||
436 | switch (dln2->irq_work[pin].type) { | ||
437 | case DLN2_GPIO_EVENT_CHANGE_RISING: | 426 | case DLN2_GPIO_EVENT_CHANGE_RISING: |
438 | if (event->value) | 427 | if (event->value) |
439 | generic_handle_irq(irq); | 428 | generic_handle_irq(irq); |
@@ -452,7 +441,7 @@ static int dln2_gpio_probe(struct platform_device *pdev) | |||
452 | struct dln2_gpio *dln2; | 441 | struct dln2_gpio *dln2; |
453 | struct device *dev = &pdev->dev; | 442 | struct device *dev = &pdev->dev; |
454 | int pins; | 443 | int pins; |
455 | int i, ret; | 444 | int ret; |
456 | 445 | ||
457 | pins = dln2_gpio_get_pin_count(pdev); | 446 | pins = dln2_gpio_get_pin_count(pdev); |
458 | if (pins < 0) { | 447 | if (pins < 0) { |
@@ -468,15 +457,7 @@ static int dln2_gpio_probe(struct platform_device *pdev) | |||
468 | if (!dln2) | 457 | if (!dln2) |
469 | return -ENOMEM; | 458 | return -ENOMEM; |
470 | 459 | ||
471 | dln2->irq_work = devm_kcalloc(&pdev->dev, pins, | 460 | mutex_init(&dln2->irq_lock); |
472 | sizeof(struct dln2_irq_work), GFP_KERNEL); | ||
473 | if (!dln2->irq_work) | ||
474 | return -ENOMEM; | ||
475 | for (i = 0; i < pins; i++) { | ||
476 | INIT_WORK(&dln2->irq_work[i].work, dln2_irq_work); | ||
477 | dln2->irq_work[i].pin = i; | ||
478 | dln2->irq_work[i].dln2 = dln2; | ||
479 | } | ||
480 | 461 | ||
481 | dln2->pdev = pdev; | 462 | dln2->pdev = pdev; |
482 | 463 | ||
@@ -530,11 +511,8 @@ out: | |||
530 | static int dln2_gpio_remove(struct platform_device *pdev) | 511 | static int dln2_gpio_remove(struct platform_device *pdev) |
531 | { | 512 | { |
532 | struct dln2_gpio *dln2 = platform_get_drvdata(pdev); | 513 | struct dln2_gpio *dln2 = platform_get_drvdata(pdev); |
533 | int i; | ||
534 | 514 | ||
535 | dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV); | 515 | dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV); |
536 | for (i = 0; i < dln2->gpio.ngpio; i++) | ||
537 | flush_work(&dln2->irq_work[i].work); | ||
538 | gpiochip_remove(&dln2->gpio); | 516 | gpiochip_remove(&dln2->gpio); |
539 | 517 | ||
540 | return 0; | 518 | return 0; |
diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c index d5bc70fce4df..35a02770c8b0 100644 --- a/drivers/gpio/gpio-grgpio.c +++ b/drivers/gpio/gpio-grgpio.c | |||
@@ -441,7 +441,8 @@ static int grgpio_probe(struct platform_device *ofdev) | |||
441 | err = gpiochip_add(gc); | 441 | err = gpiochip_add(gc); |
442 | if (err) { | 442 | if (err) { |
443 | dev_err(&ofdev->dev, "Could not add gpiochip\n"); | 443 | dev_err(&ofdev->dev, "Could not add gpiochip\n"); |
444 | irq_domain_remove(priv->domain); | 444 | if (priv->domain) |
445 | irq_domain_remove(priv->domain); | ||
445 | return err; | 446 | return err; |
446 | } | 447 | } |
447 | 448 | ||