Merge remote-tracking branch 'grant/gpio/next-mx' into devel-features

Conflicts:
	arch/arm/mach-imx/mach-mx31_3ds.c
	arch/arm/mach-imx/mach-scb9328.c

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

4 files changed, 760 insertions, 0 deletions

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 2967002a9f82..5e6fc222bb23 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -90,6 +90,15 @@ config GPIO_EXYNOS4
         def_bool y
         depends on CPU_EXYNOS4210
 
+config GPIO_MXS
+        def_bool y
+        depends on ARCH_MXS
+
+config GPIO_MXC
+        def_bool y
+        depends on ARCH_MXC
+        select GPIO_BASIC_MMIO_CORE
+
 config GPIO_PLAT_SAMSUNG
         def_bool y
         depends on SAMSUNG_GPIOLIB_4BIT
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index b605f8ec6fbe..9c37339a57a7 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -9,6 +9,8 @@ obj-$(CONFIG_GPIO_ADP5588)	+= adp5588-gpio.o
 obj-$(CONFIG_GPIO_BASIC_MMIO_CORE)      += basic_mmio_gpio.o
 obj-$(CONFIG_GPIO_BASIC_MMIO)   += basic_mmio_gpio.o
 obj-$(CONFIG_GPIO_EXYNOS4)      += gpio-exynos4.o
+obj-$(CONFIG_GPIO_MXC)          += gpio-mxc.o
+obj-$(CONFIG_GPIO_MXS)          += gpio-mxs.o
 obj-$(CONFIG_GPIO_PLAT_SAMSUNG) += gpio-plat-samsung.o
 obj-$(CONFIG_GPIO_S5PC100)      += gpio-s5pc100.o
 obj-$(CONFIG_GPIO_S5PV210)      += gpio-s5pv210.o
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
new file mode 100644
index 000000000000..b351952893bb
--- /dev/null
+++ b/drivers/gpio/gpio-mxc.c
@@ -0,0 +1,379 @@
+/*
+ * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * Based on code from Freescale,
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/basic_mmio_gpio.h>
+#include <mach/hardware.h>
+#include <asm-generic/bug.h>
+
+struct mxc_gpio_port {
+        struct list_head node;
+        void __iomem *base;
+        int irq;
+        int irq_high;
+        int virtual_irq_start;
+        struct bgpio_chip bgc;
+        u32 both_edges;
+};
+
+/*
+ * MX2 has one interrupt *for all* gpio ports. The list is used
+ * to save the references to all ports, so that mx2_gpio_irq_handler
+ * can walk through all interrupt status registers.
+ */
+static LIST_HEAD(mxc_gpio_ports);
+
+#define cpu_is_mx1_mx2()        (cpu_is_mx1() || cpu_is_mx2())
+
+#define GPIO_DR         (cpu_is_mx1_mx2() ? 0x1c : 0x00)
+#define GPIO_GDIR       (cpu_is_mx1_mx2() ? 0x00 : 0x04)
+#define GPIO_PSR        (cpu_is_mx1_mx2() ? 0x24 : 0x08)
+#define GPIO_ICR1       (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
+#define GPIO_ICR2       (cpu_is_mx1_mx2() ? 0x2C : 0x10)
+#define GPIO_IMR        (cpu_is_mx1_mx2() ? 0x30 : 0x14)
+#define GPIO_ISR        (cpu_is_mx1_mx2() ? 0x34 : 0x18)
+
+#define GPIO_INT_LOW_LEV        (cpu_is_mx1_mx2() ? 0x3 : 0x0)
+#define GPIO_INT_HIGH_LEV       (cpu_is_mx1_mx2() ? 0x2 : 0x1)
+#define GPIO_INT_RISE_EDGE      (cpu_is_mx1_mx2() ? 0x0 : 0x2)
+#define GPIO_INT_FALL_EDGE      (cpu_is_mx1_mx2() ? 0x1 : 0x3)
+#define GPIO_INT_NONE           0x4
+
+/* Note: This driver assumes 32 GPIOs are handled in one register */
+
+static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
+{
+        writel(1 << index, port->base + GPIO_ISR);
+}
+
+static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
+                                int enable)
+{
+        u32 l;
+
+        l = readl(port->base + GPIO_IMR);
+        l = (l & (~(1 << index))) | (!!enable << index);
+        writel(l, port->base + GPIO_IMR);
+}
+
+static void gpio_ack_irq(struct irq_data *d)
+{
+        struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
+        u32 gpio = irq_to_gpio(d->irq);
+        _clear_gpio_irqstatus(port, gpio & 0x1f);
+}
+
+static void gpio_mask_irq(struct irq_data *d)
+{
+        struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
+        u32 gpio = irq_to_gpio(d->irq);
+        _set_gpio_irqenable(port, gpio & 0x1f, 0);
+}
+
+static void gpio_unmask_irq(struct irq_data *d)
+{
+        struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
+        u32 gpio = irq_to_gpio(d->irq);
+        _set_gpio_irqenable(port, gpio & 0x1f, 1);
+}
+
+static int gpio_set_irq_type(struct irq_data *d, u32 type)
+{
+        u32 gpio = irq_to_gpio(d->irq);
+        struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
+        u32 bit, val;
+        int edge;
+        void __iomem *reg = port->base;
+
+        port->both_edges &= ~(1 << (gpio & 31));
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                edge = GPIO_INT_RISE_EDGE;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                edge = GPIO_INT_FALL_EDGE;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                val = gpio_get_value(gpio & 31);
+                if (val) {
+                        edge = GPIO_INT_LOW_LEV;
+                        pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
+                } else {
+                        edge = GPIO_INT_HIGH_LEV;
+                        pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
+                }
+                port->both_edges |= 1 << (gpio & 31);
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                edge = GPIO_INT_LOW_LEV;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                edge = GPIO_INT_HIGH_LEV;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
+        bit = gpio & 0xf;
+        val = readl(reg) & ~(0x3 << (bit << 1));
+        writel(val | (edge << (bit << 1)), reg);
+        _clear_gpio_irqstatus(port, gpio & 0x1f);
+
+        return 0;
+}
+
+static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
+{
+        void __iomem *reg = port->base;
+        u32 bit, val;
+        int edge;
+
+        reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
+        bit = gpio & 0xf;
+        val = readl(reg);
+        edge = (val >> (bit << 1)) & 3;
+        val &= ~(0x3 << (bit << 1));
+        if (edge == GPIO_INT_HIGH_LEV) {
+                edge = GPIO_INT_LOW_LEV;
+                pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
+        } else if (edge == GPIO_INT_LOW_LEV) {
+                edge = GPIO_INT_HIGH_LEV;
+                pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
+        } else {
+                pr_err("mxc: invalid configuration for GPIO %d: %x\n",
+                       gpio, edge);
+                return;
+        }
+        writel(val | (edge << (bit << 1)), reg);
+}
+
+/* handle 32 interrupts in one status register */
+static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
+{
+        u32 gpio_irq_no_base = port->virtual_irq_start;
+
+        while (irq_stat != 0) {
+                int irqoffset = fls(irq_stat) - 1;
+
+                if (port->both_edges & (1 << irqoffset))
+                        mxc_flip_edge(port, irqoffset);
+
+                generic_handle_irq(gpio_irq_no_base + irqoffset);
+
+                irq_stat &= ~(1 << irqoffset);
+        }
+}
+
+/* MX1 and MX3 has one interrupt *per* gpio port */
+static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+        u32 irq_stat;
+        struct mxc_gpio_port *port = irq_get_handler_data(irq);
+
+        irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
+
+        mxc_gpio_irq_handler(port, irq_stat);
+}
+
+/* MX2 has one interrupt *for all* gpio ports */
+static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+        u32 irq_msk, irq_stat;
+        struct mxc_gpio_port *port;
+
+        /* walk through all interrupt status registers */
+        list_for_each_entry(port, &mxc_gpio_ports, node) {
+                irq_msk = readl(port->base + GPIO_IMR);
+                if (!irq_msk)
+                        continue;
+
+                irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
+                if (irq_stat)
+                        mxc_gpio_irq_handler(port, irq_stat);
+        }
+}
+
+/*
+ * Set interrupt number "irq" in the GPIO as a wake-up source.
+ * While system is running, all registered GPIO interrupts need to have
+ * wake-up enabled. When system is suspended, only selected GPIO interrupts
+ * need to have wake-up enabled.
+ * @param  irq          interrupt source number
+ * @param  enable       enable as wake-up if equal to non-zero
+ * @return       This function returns 0 on success.
+ */
+static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
+{
+        u32 gpio = irq_to_gpio(d->irq);
+        u32 gpio_idx = gpio & 0x1F;
+        struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
+
+        if (enable) {
+                if (port->irq_high && (gpio_idx >= 16))
+                        enable_irq_wake(port->irq_high);
+                else
+                        enable_irq_wake(port->irq);
+        } else {
+                if (port->irq_high && (gpio_idx >= 16))
+                        disable_irq_wake(port->irq_high);
+                else
+                        disable_irq_wake(port->irq);
+        }
+
+        return 0;
+}
+
+static struct irq_chip gpio_irq_chip = {
+        .name = "GPIO",
+        .irq_ack = gpio_ack_irq,
+        .irq_mask = gpio_mask_irq,
+        .irq_unmask = gpio_unmask_irq,
+        .irq_set_type = gpio_set_irq_type,
+        .irq_set_wake = gpio_set_wake_irq,
+};
+
+/*
+ * This lock class tells lockdep that GPIO irqs are in a different
+ * category than their parents, so it won't report false recursion.
+ */
+static struct lock_class_key gpio_lock_class;
+
+static int __devinit mxc_gpio_probe(struct platform_device *pdev)
+{
+        struct mxc_gpio_port *port;
+        struct resource *iores;
+        int err, i;
+
+        port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
+        if (!port)
+                return -ENOMEM;
+
+        port->virtual_irq_start = MXC_GPIO_IRQ_START + pdev->id * 32;
+
+        iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!iores) {
+                err = -ENODEV;
+                goto out_kfree;
+        }
+
+        if (!request_mem_region(iores->start, resource_size(iores),
+                                pdev->name)) {
+                err = -EBUSY;
+                goto out_kfree;
+        }
+
+        port->base = ioremap(iores->start, resource_size(iores));
+        if (!port->base) {
+                err = -ENOMEM;
+                goto out_release_mem;
+        }
+
+        port->irq_high = platform_get_irq(pdev, 1);
+        port->irq = platform_get_irq(pdev, 0);
+        if (port->irq < 0) {
+                err = -EINVAL;
+                goto out_iounmap;
+        }
+
+        /* disable the interrupt and clear the status */
+        writel(0, port->base + GPIO_IMR);
+        writel(~0, port->base + GPIO_ISR);
+
+        for (i = port->virtual_irq_start;
+                i < port->virtual_irq_start + 32; i++) {
+                irq_set_lockdep_class(i, &gpio_lock_class);
+                irq_set_chip_and_handler(i, &gpio_irq_chip, handle_level_irq);
+                set_irq_flags(i, IRQF_VALID);
+                irq_set_chip_data(i, port);
+        }
+
+        if (cpu_is_mx2()) {
+                /* setup one handler for all GPIO interrupts */
+                if (pdev->id == 0)
+                        irq_set_chained_handler(port->irq,
+                                                mx2_gpio_irq_handler);
+        } else {
+                /* setup one handler for each entry */
+                irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
+                irq_set_handler_data(port->irq, port);
+                if (port->irq_high > 0) {
+                        /* setup handler for GPIO 16 to 31 */
+                        irq_set_chained_handler(port->irq_high,
+                                                mx3_gpio_irq_handler);
+                        irq_set_handler_data(port->irq_high, port);
+                }
+        }
+
+        err = bgpio_init(&port->bgc, &pdev->dev, 4,
+                         port->base + GPIO_PSR,
+                         port->base + GPIO_DR, NULL,
+                         port->base + GPIO_GDIR, NULL, false);
+        if (err)
+                goto out_iounmap;
+
+        port->bgc.gc.base = pdev->id * 32;
+
+        err = gpiochip_add(&port->bgc.gc);
+        if (err)
+                goto out_bgpio_remove;
+
+        list_add_tail(&port->node, &mxc_gpio_ports);
+
+        return 0;
+
+out_bgpio_remove:
+        bgpio_remove(&port->bgc);
+out_iounmap:
+        iounmap(port->base);
+out_release_mem:
+        release_mem_region(iores->start, resource_size(iores));
+out_kfree:
+        kfree(port);
+        dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
+        return err;
+}
+
+static struct platform_driver mxc_gpio_driver = {
+        .driver         = {
+                .name   = "gpio-mxc",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = mxc_gpio_probe,
+};
+
+static int __init gpio_mxc_init(void)
+{
+        return platform_driver_register(&mxc_gpio_driver);
+}
+postcore_initcall(gpio_mxc_init);
+
+MODULE_AUTHOR("Freescale Semiconductor, "
+              "Daniel Mack <danielncaiaq.de>, "
+              "Juergen Beisert <kernel@pengutronix.de>");
+MODULE_DESCRIPTION("Freescale MXC GPIO");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
new file mode 100644
index 000000000000..a28761428bb0
--- /dev/null
+++ b/drivers/gpio/gpio-mxs.c
@@ -0,0 +1,370 @@
+/*
+ * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * Based on code from Freescale,
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <mach/mxs.h>
+
+#define MXS_SET         0x4
+#define MXS_CLR         0x8
+
+#define PINCTRL_DOUT(n)         ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
+#define PINCTRL_DIN(n)          ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
+#define PINCTRL_DOE(n)          ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
+#define PINCTRL_PIN2IRQ(n)      ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
+#define PINCTRL_IRQEN(n)        ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
+#define PINCTRL_IRQLEV(n)       ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
+#define PINCTRL_IRQPOL(n)       ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
+#define PINCTRL_IRQSTAT(n)      ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
+
+#define GPIO_INT_FALL_EDGE      0x0
+#define GPIO_INT_LOW_LEV        0x1
+#define GPIO_INT_RISE_EDGE      0x2
+#define GPIO_INT_HIGH_LEV       0x3
+#define GPIO_INT_LEV_MASK       (1 << 0)
+#define GPIO_INT_POL_MASK       (1 << 1)
+
+struct mxs_gpio_port {
+        void __iomem *base;
+        int id;
+        int irq;
+        int irq_high;
+        int virtual_irq_start;
+        struct gpio_chip chip;
+};
+
+/* Note: This driver assumes 32 GPIOs are handled in one register */
+
+static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
+{
+        writel(1 << index, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
+}
+
+static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
+                                int enable)
+{
+        if (enable) {
+                writel(1 << index,
+                        port->base + PINCTRL_IRQEN(port->id) + MXS_SET);
+                writel(1 << index,
+                        port->base + PINCTRL_PIN2IRQ(port->id) + MXS_SET);
+        } else {
+                writel(1 << index,
+                        port->base + PINCTRL_IRQEN(port->id) + MXS_CLR);
+        }
+}
+
+static void mxs_gpio_ack_irq(struct irq_data *d)
+{
+        struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
+        u32 gpio = irq_to_gpio(d->irq);
+        clear_gpio_irqstatus(port, gpio & 0x1f);
+}
+
+static void mxs_gpio_mask_irq(struct irq_data *d)
+{
+        struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
+        u32 gpio = irq_to_gpio(d->irq);
+        set_gpio_irqenable(port, gpio & 0x1f, 0);
+}
+
+static void mxs_gpio_unmask_irq(struct irq_data *d)
+{
+        struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
+        u32 gpio = irq_to_gpio(d->irq);
+        set_gpio_irqenable(port, gpio & 0x1f, 1);
+}
+
+static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset);
+
+static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
+{
+        u32 gpio = irq_to_gpio(d->irq);
+        u32 pin_mask = 1 << (gpio & 31);
+        struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
+        void __iomem *pin_addr;
+        int edge;
+
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                edge = GPIO_INT_RISE_EDGE;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                edge = GPIO_INT_FALL_EDGE;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                edge = GPIO_INT_LOW_LEV;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                edge = GPIO_INT_HIGH_LEV;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* set level or edge */
+        pin_addr = port->base + PINCTRL_IRQLEV(port->id);
+        if (edge & GPIO_INT_LEV_MASK)
+                writel(pin_mask, pin_addr + MXS_SET);
+        else
+                writel(pin_mask, pin_addr + MXS_CLR);
+
+        /* set polarity */
+        pin_addr = port->base + PINCTRL_IRQPOL(port->id);
+        if (edge & GPIO_INT_POL_MASK)
+                writel(pin_mask, pin_addr + MXS_SET);
+        else
+                writel(pin_mask, pin_addr + MXS_CLR);
+
+        clear_gpio_irqstatus(port, gpio & 0x1f);
+
+        return 0;
+}
+
+/* MXS has one interrupt *per* gpio port */
+static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+        u32 irq_stat;
+        struct mxs_gpio_port *port = irq_get_handler_data(irq);
+        u32 gpio_irq_no_base = port->virtual_irq_start;
+
+        desc->irq_data.chip->irq_ack(&desc->irq_data);
+
+        irq_stat = readl(port->base + PINCTRL_IRQSTAT(port->id)) &
+                        readl(port->base + PINCTRL_IRQEN(port->id));
+
+        while (irq_stat != 0) {
+                int irqoffset = fls(irq_stat) - 1;
+                generic_handle_irq(gpio_irq_no_base + irqoffset);
+                irq_stat &= ~(1 << irqoffset);
+        }
+}
+
+/*
+ * Set interrupt number "irq" in the GPIO as a wake-up source.
+ * While system is running, all registered GPIO interrupts need to have
+ * wake-up enabled. When system is suspended, only selected GPIO interrupts
+ * need to have wake-up enabled.
+ * @param  irq          interrupt source number
+ * @param  enable       enable as wake-up if equal to non-zero
+ * @return       This function returns 0 on success.
+ */
+static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
+{
+        u32 gpio = irq_to_gpio(d->irq);
+        u32 gpio_idx = gpio & 0x1f;
+        struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
+
+        if (enable) {
+                if (port->irq_high && (gpio_idx >= 16))
+                        enable_irq_wake(port->irq_high);
+                else
+                        enable_irq_wake(port->irq);
+        } else {
+                if (port->irq_high && (gpio_idx >= 16))
+                        disable_irq_wake(port->irq_high);
+                else
+                        disable_irq_wake(port->irq);
+        }
+
+        return 0;
+}
+
+static struct irq_chip gpio_irq_chip = {
+        .name = "mxs gpio",
+        .irq_ack = mxs_gpio_ack_irq,
+        .irq_mask = mxs_gpio_mask_irq,
+        .irq_unmask = mxs_gpio_unmask_irq,
+        .irq_set_type = mxs_gpio_set_irq_type,
+        .irq_set_wake = mxs_gpio_set_wake_irq,
+};
+
+static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset,
+                                int dir)
+{
+        struct mxs_gpio_port *port =
+                container_of(chip, struct mxs_gpio_port, chip);
+        void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id);
+
+        if (dir)
+                writel(1 << offset, pin_addr + MXS_SET);
+        else
+                writel(1 << offset, pin_addr + MXS_CLR);
+}
+
+static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct mxs_gpio_port *port =
+                container_of(chip, struct mxs_gpio_port, chip);
+
+        return (readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1;
+}
+
+static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct mxs_gpio_port *port =
+                container_of(chip, struct mxs_gpio_port, chip);
+        void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id);
+
+        if (value)
+                writel(1 << offset, pin_addr + MXS_SET);
+        else
+                writel(1 << offset, pin_addr + MXS_CLR);
+}
+
+static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        struct mxs_gpio_port *port =
+                container_of(chip, struct mxs_gpio_port, chip);
+
+        return port->virtual_irq_start + offset;
+}
+
+static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        mxs_set_gpio_direction(chip, offset, 0);
+        return 0;
+}
+
+static int mxs_gpio_direction_output(struct gpio_chip *chip,
+                                     unsigned offset, int value)
+{
+        mxs_gpio_set(chip, offset, value);
+        mxs_set_gpio_direction(chip, offset, 1);
+        return 0;
+}
+
+static int __devinit mxs_gpio_probe(struct platform_device *pdev)
+{
+        static void __iomem *base;
+        struct mxs_gpio_port *port;
+        struct resource *iores = NULL;
+        int err, i;
+
+        port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);
+        if (!port)
+                return -ENOMEM;
+
+        port->id = pdev->id;
+        port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
+
+        /*
+         * map memory region only once, as all the gpio ports
+         * share the same one
+         */
+        if (!base) {
+                iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+                if (!iores) {
+                        err = -ENODEV;
+                        goto out_kfree;
+                }
+
+                if (!request_mem_region(iores->start, resource_size(iores),
+                                        pdev->name)) {
+                        err = -EBUSY;
+                        goto out_kfree;
+                }
+
+                base = ioremap(iores->start, resource_size(iores));
+                if (!base) {
+                        err = -ENOMEM;
+                        goto out_release_mem;
+                }
+        }
+        port->base = base;
+
+        port->irq = platform_get_irq(pdev, 0);
+        if (port->irq < 0) {
+                err = -EINVAL;
+                goto out_iounmap;
+        }
+
+        /* disable the interrupt and clear the status */
+        writel(0, port->base + PINCTRL_PIN2IRQ(port->id));
+        writel(0, port->base + PINCTRL_IRQEN(port->id));
+
+        /* clear address has to be used to clear IRQSTAT bits */
+        writel(~0U, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
+
+        for (i = port->virtual_irq_start;
+                i < port->virtual_irq_start + 32; i++) {
+                irq_set_chip_and_handler(i, &gpio_irq_chip,
+                                         handle_level_irq);
+                set_irq_flags(i, IRQF_VALID);
+                irq_set_chip_data(i, port);
+        }
+
+        /* setup one handler for each entry */
+        irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
+        irq_set_handler_data(port->irq, port);
+
+        /* register gpio chip */
+        port->chip.direction_input = mxs_gpio_direction_input;
+        port->chip.direction_output = mxs_gpio_direction_output;
+        port->chip.get = mxs_gpio_get;
+        port->chip.set = mxs_gpio_set;
+        port->chip.to_irq = mxs_gpio_to_irq;
+        port->chip.base = port->id * 32;
+        port->chip.ngpio = 32;
+
+        err = gpiochip_add(&port->chip);
+        if (err)
+                goto out_iounmap;
+
+        return 0;
+
+out_iounmap:
+        if (iores)
+                iounmap(port->base);
+out_release_mem:
+        if (iores)
+                release_mem_region(iores->start, resource_size(iores));
+out_kfree:
+        kfree(port);
+        dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
+        return err;
+}
+
+static struct platform_driver mxs_gpio_driver = {
+        .driver         = {
+                .name   = "gpio-mxs",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = mxs_gpio_probe,
+};
+
+static int __init mxs_gpio_init(void)
+{
+        return platform_driver_register(&mxs_gpio_driver);
+}
+postcore_initcall(mxs_gpio_init);
+
+MODULE_AUTHOR("Freescale Semiconductor, "
+              "Daniel Mack <danielncaiaq.de>, "
+              "Juergen Beisert <kernel@pengutronix.de>");
+MODULE_DESCRIPTION("Freescale MXS GPIO");
+MODULE_LICENSE("GPL");