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authorLinus Torvalds <torvalds@linux-foundation.org>2014-08-08 14:14:29 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-08-08 14:14:29 -0400
commitb3345d7c57d70e6cb6749af25cdbe80515582e99 (patch)
tree04cce706bc7e944ad1fb257108a8ae735948f97f /drivers/gpio
parent44c916d58b9ef1f2c4aec2def57fa8289c716a60 (diff)
parentc2fff85e21818952aa0ee5778926beee6c03e579 (diff)
Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson: "This is the bulk of new SoC enablement and other platform changes for 3.17: - Samsung S5PV210 has been converted to DT and multiplatform - Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms - Kirkwood, one of the popular Marvell platforms, is folded into the mvebu platform code, removing mach-kirkwood - Hwmod data for TI AM43xx and DRA7 platforms - More additions of Renesas shmobile platform support - Removal of plat-samsung contents that can be removed with S5PV210 being multiplatform/DT-enabled and the other two old platforms being removed New platforms (most with only basic support right now): - Hisilicon X5HD2 settop box chipset is introduced - Mediatek MT6589 (mobile chipset) is introduced - Broadcom BCM7xxx settop box chipset is introduced + as usual a lot other pieces all over the platform code" * tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits) ARM: hisi: remove smp from machine descriptor power: reset: move hisilicon reboot code ARM: dts: Add hix5hd2-dkb dts file. ARM: debug: Rename Hi3716 to HIX5HD2 ARM: hisi: enable hix5hd2 SoC ARM: hisi: add ARCH_HISI MAINTAINERS: add entry for Broadcom ARM STB architecture ARM: brcmstb: select GISB arbiter and interrupt drivers ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs ARM: configs: enable SMP in bcm_defconfig ARM: add SMP support for Broadcom mobile SoCs Documentation: arm: misc updates to Marvell EBU SoC status Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC ARM: mvebu: fix build without platforms selected ARM: mvebu: add cpuidle support for Armada 38x ARM: mvebu: add cpuidle support for Armada 370 cpuidle: mvebu: add Armada 38x support cpuidle: mvebu: add Armada 370 support cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7 ARM: mvebu: export the SCU address ...
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/gpio-samsung.c240
1 files changed, 0 insertions, 240 deletions
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index d9cff026827e..3810da47043f 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -1166,234 +1166,9 @@ static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1166#endif 1166#endif
1167}; 1167};
1168 1168
1169/*
1170 * Followings are the gpio banks in S5PV210/S5PC110
1171 *
1172 * The 'config' member when left to NULL, is initialized to the default
1173 * structure samsung_gpio_cfgs[3] in the init function below.
1174 *
1175 * The 'base' member is also initialized in the init function below.
1176 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1177 * uses the above macro and depends on the banks being listed in order here.
1178 */
1179
1180static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1181#ifdef CONFIG_CPU_S5PV210
1182 {
1183 .chip = {
1184 .base = S5PV210_GPA0(0),
1185 .ngpio = S5PV210_GPIO_A0_NR,
1186 .label = "GPA0",
1187 },
1188 }, {
1189 .chip = {
1190 .base = S5PV210_GPA1(0),
1191 .ngpio = S5PV210_GPIO_A1_NR,
1192 .label = "GPA1",
1193 },
1194 }, {
1195 .chip = {
1196 .base = S5PV210_GPB(0),
1197 .ngpio = S5PV210_GPIO_B_NR,
1198 .label = "GPB",
1199 },
1200 }, {
1201 .chip = {
1202 .base = S5PV210_GPC0(0),
1203 .ngpio = S5PV210_GPIO_C0_NR,
1204 .label = "GPC0",
1205 },
1206 }, {
1207 .chip = {
1208 .base = S5PV210_GPC1(0),
1209 .ngpio = S5PV210_GPIO_C1_NR,
1210 .label = "GPC1",
1211 },
1212 }, {
1213 .chip = {
1214 .base = S5PV210_GPD0(0),
1215 .ngpio = S5PV210_GPIO_D0_NR,
1216 .label = "GPD0",
1217 },
1218 }, {
1219 .chip = {
1220 .base = S5PV210_GPD1(0),
1221 .ngpio = S5PV210_GPIO_D1_NR,
1222 .label = "GPD1",
1223 },
1224 }, {
1225 .chip = {
1226 .base = S5PV210_GPE0(0),
1227 .ngpio = S5PV210_GPIO_E0_NR,
1228 .label = "GPE0",
1229 },
1230 }, {
1231 .chip = {
1232 .base = S5PV210_GPE1(0),
1233 .ngpio = S5PV210_GPIO_E1_NR,
1234 .label = "GPE1",
1235 },
1236 }, {
1237 .chip = {
1238 .base = S5PV210_GPF0(0),
1239 .ngpio = S5PV210_GPIO_F0_NR,
1240 .label = "GPF0",
1241 },
1242 }, {
1243 .chip = {
1244 .base = S5PV210_GPF1(0),
1245 .ngpio = S5PV210_GPIO_F1_NR,
1246 .label = "GPF1",
1247 },
1248 }, {
1249 .chip = {
1250 .base = S5PV210_GPF2(0),
1251 .ngpio = S5PV210_GPIO_F2_NR,
1252 .label = "GPF2",
1253 },
1254 }, {
1255 .chip = {
1256 .base = S5PV210_GPF3(0),
1257 .ngpio = S5PV210_GPIO_F3_NR,
1258 .label = "GPF3",
1259 },
1260 }, {
1261 .chip = {
1262 .base = S5PV210_GPG0(0),
1263 .ngpio = S5PV210_GPIO_G0_NR,
1264 .label = "GPG0",
1265 },
1266 }, {
1267 .chip = {
1268 .base = S5PV210_GPG1(0),
1269 .ngpio = S5PV210_GPIO_G1_NR,
1270 .label = "GPG1",
1271 },
1272 }, {
1273 .chip = {
1274 .base = S5PV210_GPG2(0),
1275 .ngpio = S5PV210_GPIO_G2_NR,
1276 .label = "GPG2",
1277 },
1278 }, {
1279 .chip = {
1280 .base = S5PV210_GPG3(0),
1281 .ngpio = S5PV210_GPIO_G3_NR,
1282 .label = "GPG3",
1283 },
1284 }, {
1285 .chip = {
1286 .base = S5PV210_GPI(0),
1287 .ngpio = S5PV210_GPIO_I_NR,
1288 .label = "GPI",
1289 },
1290 }, {
1291 .chip = {
1292 .base = S5PV210_GPJ0(0),
1293 .ngpio = S5PV210_GPIO_J0_NR,
1294 .label = "GPJ0",
1295 },
1296 }, {
1297 .chip = {
1298 .base = S5PV210_GPJ1(0),
1299 .ngpio = S5PV210_GPIO_J1_NR,
1300 .label = "GPJ1",
1301 },
1302 }, {
1303 .chip = {
1304 .base = S5PV210_GPJ2(0),
1305 .ngpio = S5PV210_GPIO_J2_NR,
1306 .label = "GPJ2",
1307 },
1308 }, {
1309 .chip = {
1310 .base = S5PV210_GPJ3(0),
1311 .ngpio = S5PV210_GPIO_J3_NR,
1312 .label = "GPJ3",
1313 },
1314 }, {
1315 .chip = {
1316 .base = S5PV210_GPJ4(0),
1317 .ngpio = S5PV210_GPIO_J4_NR,
1318 .label = "GPJ4",
1319 },
1320 }, {
1321 .chip = {
1322 .base = S5PV210_MP01(0),
1323 .ngpio = S5PV210_GPIO_MP01_NR,
1324 .label = "MP01",
1325 },
1326 }, {
1327 .chip = {
1328 .base = S5PV210_MP02(0),
1329 .ngpio = S5PV210_GPIO_MP02_NR,
1330 .label = "MP02",
1331 },
1332 }, {
1333 .chip = {
1334 .base = S5PV210_MP03(0),
1335 .ngpio = S5PV210_GPIO_MP03_NR,
1336 .label = "MP03",
1337 },
1338 }, {
1339 .chip = {
1340 .base = S5PV210_MP04(0),
1341 .ngpio = S5PV210_GPIO_MP04_NR,
1342 .label = "MP04",
1343 },
1344 }, {
1345 .chip = {
1346 .base = S5PV210_MP05(0),
1347 .ngpio = S5PV210_GPIO_MP05_NR,
1348 .label = "MP05",
1349 },
1350 }, {
1351 .base = (S5P_VA_GPIO + 0xC00),
1352 .irq_base = IRQ_EINT(0),
1353 .chip = {
1354 .base = S5PV210_GPH0(0),
1355 .ngpio = S5PV210_GPIO_H0_NR,
1356 .label = "GPH0",
1357 .to_irq = samsung_gpiolib_to_irq,
1358 },
1359 }, {
1360 .base = (S5P_VA_GPIO + 0xC20),
1361 .irq_base = IRQ_EINT(8),
1362 .chip = {
1363 .base = S5PV210_GPH1(0),
1364 .ngpio = S5PV210_GPIO_H1_NR,
1365 .label = "GPH1",
1366 .to_irq = samsung_gpiolib_to_irq,
1367 },
1368 }, {
1369 .base = (S5P_VA_GPIO + 0xC40),
1370 .irq_base = IRQ_EINT(16),
1371 .chip = {
1372 .base = S5PV210_GPH2(0),
1373 .ngpio = S5PV210_GPIO_H2_NR,
1374 .label = "GPH2",
1375 .to_irq = samsung_gpiolib_to_irq,
1376 },
1377 }, {
1378 .base = (S5P_VA_GPIO + 0xC60),
1379 .irq_base = IRQ_EINT(24),
1380 .chip = {
1381 .base = S5PV210_GPH3(0),
1382 .ngpio = S5PV210_GPIO_H3_NR,
1383 .label = "GPH3",
1384 .to_irq = samsung_gpiolib_to_irq,
1385 },
1386 },
1387#endif
1388};
1389
1390/* TODO: cleanup soc_is_* */ 1169/* TODO: cleanup soc_is_* */
1391static __init int samsung_gpiolib_init(void) 1170static __init int samsung_gpiolib_init(void)
1392{ 1171{
1393 struct samsung_gpio_chip *chip;
1394 int i, nr_chips;
1395 int group = 0;
1396
1397 /* 1172 /*
1398 * Currently there are two drivers that can provide GPIO support for 1173 * Currently there are two drivers that can provide GPIO support for
1399 * Samsung SoCs. For device tree enabled platforms, the new 1174 * Samsung SoCs. For device tree enabled platforms, the new
@@ -1417,21 +1192,6 @@ static __init int samsung_gpiolib_init(void)
1417 S3C64XX_VA_GPIO); 1192 S3C64XX_VA_GPIO);
1418 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2, 1193 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
1419 ARRAY_SIZE(s3c64xx_gpios_4bit2)); 1194 ARRAY_SIZE(s3c64xx_gpios_4bit2));
1420 } else if (soc_is_s5pv210()) {
1421 group = 0;
1422 chip = s5pv210_gpios_4bit;
1423 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
1424
1425 for (i = 0; i < nr_chips; i++, chip++) {
1426 if (!chip->config) {
1427 chip->config = &samsung_gpio_cfgs[3];
1428 chip->group = group++;
1429 }
1430 }
1431 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
1432#if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
1433 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
1434#endif
1435 } else { 1195 } else {
1436 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n"); 1196 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
1437 return -ENODEV; 1197 return -ENODEV;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 05:48:46 -0500