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authorLinus Torvalds <torvalds@linux-foundation.org>2011-05-28 13:56:34 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-05-28 13:56:34 -0400
commit04830fccdcafa7e0ea913990ae56437253553fef (patch)
tree16d423628a516f544a0e5bb8fd4f00d88a55395f /drivers/gpio
parent571503e10045c89af951962ea0bb783482663aad (diff)
parent1486a7409b42ec434be310e091ef68660a2f6cd0 (diff)
Merge branch 'gpio/next' of git://git.secretlab.ca/git/linux-2.6
* 'gpio/next' of git://git.secretlab.ca/git/linux-2.6: gpio/pch_gpio: Support new device ML7223 gpio: make gpio_{request,free}_array gpio array parameter const GPIO: OMAP: move to drivers/gpio GPIO: OMAP: move register offset defines into <plat/gpio.h> gpio: Convert gpio_is_valid to return bool gpio: Move the s5pc100 GPIO to drivers/gpio gpio: Move the s5pv210 GPIO to drivers/gpio gpio: Move the exynos4 GPIO to drivers/gpio gpio: Move to Samsung common GPIO library to drivers/gpio gpio/nomadik: add function to read GPIO pull down status gpio/nomadik: show all pins in debug gpio: move Nomadik GPIO driver to drivers/gpio gpio: move U300 GPIO driver to drivers/gpio langwell_gpio: add runtime pm support gpio/pca953x: Add support for pca9574 and pca9575 devices gpio/cs5535: Show explicit dependency between gpio_cs5535 and mfd_cs5535
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/Kconfig34
-rw-r--r--drivers/gpio/Makefile7
-rw-r--r--drivers/gpio/gpio-exynos4.c365
-rw-r--r--drivers/gpio/gpio-nomadik.c1069
-rw-r--r--drivers/gpio/gpio-omap.c2007
-rw-r--r--drivers/gpio/gpio-plat-samsung.c206
-rw-r--r--drivers/gpio/gpio-s5pc100.c355
-rw-r--r--drivers/gpio/gpio-s5pv210.c288
-rw-r--r--drivers/gpio/gpio-u300.c700
-rw-r--r--drivers/gpio/gpiolib.c4
-rw-r--r--drivers/gpio/langwell_gpio.c65
-rw-r--r--drivers/gpio/pca953x.c249
-rw-r--r--drivers/gpio/pch_gpio.c2
13 files changed, 5289 insertions, 62 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d21364603755..592397629ddc 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -86,6 +86,30 @@ config GPIO_IT8761E
86 help 86 help
87 Say yes here to support GPIO functionality of IT8761E super I/O chip. 87 Say yes here to support GPIO functionality of IT8761E super I/O chip.
88 88
89config GPIO_EXYNOS4
90 bool "Samsung Exynos4 GPIO library support"
91 default y if CPU_EXYNOS4210
92 help
93 Say yes here to support Samsung Exynos4 series SoCs GPIO library
94
95config GPIO_PLAT_SAMSUNG
96 bool "Samsung SoCs GPIO library support"
97 default y if SAMSUNG_GPIOLIB_4BIT
98 help
99 Say yes here to support Samsung SoCs GPIO library
100
101config GPIO_S5PC100
102 bool "Samsung S5PC100 GPIO library support"
103 default y if CPU_S5PC100
104 help
105 Say yes here to support Samsung S5PC100 SoCs GPIO library
106
107config GPIO_S5PV210
108 bool "Samsung S5PV210/S5PC110 GPIO library support"
109 default y if CPU_S5PV210
110 help
111 Say yes here to support Samsung S5PV210/S5PC110 SoCs GPIO library
112
89config GPIO_PL061 113config GPIO_PL061
90 bool "PrimeCell PL061 GPIO support" 114 bool "PrimeCell PL061 GPIO support"
91 depends on ARM_AMBA 115 depends on ARM_AMBA
@@ -303,7 +327,7 @@ comment "PCI GPIO expanders:"
303 327
304config GPIO_CS5535 328config GPIO_CS5535
305 tristate "AMD CS5535/CS5536 GPIO support" 329 tristate "AMD CS5535/CS5536 GPIO support"
306 depends on PCI && X86 && !CS5535_GPIO 330 depends on PCI && X86 && !CS5535_GPIO && MFD_CS5535
307 help 331 help
308 The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that 332 The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that
309 can be used for quite a number of things. The CS5535/6 is found on 333 can be used for quite a number of things. The CS5535/6 is found on
@@ -334,13 +358,19 @@ config GPIO_LANGWELL
334 Say Y here to support Intel Langwell/Penwell GPIO. 358 Say Y here to support Intel Langwell/Penwell GPIO.
335 359
336config GPIO_PCH 360config GPIO_PCH
337 tristate "PCH GPIO of Intel Topcliff" 361 tristate "Intel EG20T PCH / OKI SEMICONDUCTOR ML7223 IOH GPIO"
338 depends on PCI && X86 362 depends on PCI && X86
339 help 363 help
340 This driver is for PCH(Platform controller Hub) GPIO of Intel Topcliff 364 This driver is for PCH(Platform controller Hub) GPIO of Intel Topcliff
341 which is an IOH(Input/Output Hub) for x86 embedded processor. 365 which is an IOH(Input/Output Hub) for x86 embedded processor.
342 This driver can access PCH GPIO device. 366 This driver can access PCH GPIO device.
343 367
368 This driver also can be used for OKI SEMICONDUCTOR IOH(Input/
369 Output Hub), ML7223.
370 ML7223 IOH is for MP(Media Phone) use.
371 ML7223 is companion chip for Intel Atom E6xx series.
372 ML7223 is completely compatible for Intel EG20T PCH.
373
344config GPIO_ML_IOH 374config GPIO_ML_IOH
345 tristate "OKI SEMICONDUCTOR ML7213 IOH GPIO support" 375 tristate "OKI SEMICONDUCTOR ML7213 IOH GPIO support"
346 depends on PCI 376 depends on PCI
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 6a3387acc0e5..b605f8ec6fbe 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -8,6 +8,10 @@ obj-$(CONFIG_GPIO_ADP5520) += adp5520-gpio.o
8obj-$(CONFIG_GPIO_ADP5588) += adp5588-gpio.o 8obj-$(CONFIG_GPIO_ADP5588) += adp5588-gpio.o
9obj-$(CONFIG_GPIO_BASIC_MMIO_CORE) += basic_mmio_gpio.o 9obj-$(CONFIG_GPIO_BASIC_MMIO_CORE) += basic_mmio_gpio.o
10obj-$(CONFIG_GPIO_BASIC_MMIO) += basic_mmio_gpio.o 10obj-$(CONFIG_GPIO_BASIC_MMIO) += basic_mmio_gpio.o
11obj-$(CONFIG_GPIO_EXYNOS4) += gpio-exynos4.o
12obj-$(CONFIG_GPIO_PLAT_SAMSUNG) += gpio-plat-samsung.o
13obj-$(CONFIG_GPIO_S5PC100) += gpio-s5pc100.o
14obj-$(CONFIG_GPIO_S5PV210) += gpio-s5pv210.o
11obj-$(CONFIG_GPIO_LANGWELL) += langwell_gpio.o 15obj-$(CONFIG_GPIO_LANGWELL) += langwell_gpio.o
12obj-$(CONFIG_GPIO_MAX730X) += max730x.o 16obj-$(CONFIG_GPIO_MAX730X) += max730x.o
13obj-$(CONFIG_GPIO_MAX7300) += max7300.o 17obj-$(CONFIG_GPIO_MAX7300) += max7300.o
@@ -16,6 +20,7 @@ obj-$(CONFIG_GPIO_MAX732X) += max732x.o
16obj-$(CONFIG_GPIO_MC33880) += mc33880.o 20obj-$(CONFIG_GPIO_MC33880) += mc33880.o
17obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o 21obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o
18obj-$(CONFIG_GPIO_74X164) += 74x164.o 22obj-$(CONFIG_GPIO_74X164) += 74x164.o
23obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o
19obj-$(CONFIG_GPIO_PCA953X) += pca953x.o 24obj-$(CONFIG_GPIO_PCA953X) += pca953x.o
20obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o 25obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o
21obj-$(CONFIG_GPIO_PCH) += pch_gpio.o 26obj-$(CONFIG_GPIO_PCH) += pch_gpio.o
@@ -34,6 +39,8 @@ obj-$(CONFIG_GPIO_WM831X) += wm831x-gpio.o
34obj-$(CONFIG_GPIO_WM8350) += wm8350-gpiolib.o 39obj-$(CONFIG_GPIO_WM8350) += wm8350-gpiolib.o
35obj-$(CONFIG_GPIO_WM8994) += wm8994-gpio.o 40obj-$(CONFIG_GPIO_WM8994) += wm8994-gpio.o
36obj-$(CONFIG_GPIO_SCH) += sch_gpio.o 41obj-$(CONFIG_GPIO_SCH) += sch_gpio.o
42obj-$(CONFIG_MACH_U300) += gpio-u300.o
43obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o
37obj-$(CONFIG_GPIO_RDC321X) += rdc321x-gpio.o 44obj-$(CONFIG_GPIO_RDC321X) += rdc321x-gpio.o
38obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o 45obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o
39obj-$(CONFIG_GPIO_SX150X) += sx150x.o 46obj-$(CONFIG_GPIO_SX150X) += sx150x.o
diff --git a/drivers/gpio/gpio-exynos4.c b/drivers/gpio/gpio-exynos4.c
new file mode 100644
index 000000000000..d54ca6adb660
--- /dev/null
+++ b/drivers/gpio/gpio-exynos4.c
@@ -0,0 +1,365 @@
1/* linux/arch/arm/mach-exynos4/gpiolib.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17
18#include <mach/map.h>
19
20#include <plat/gpio-core.h>
21#include <plat/gpio-cfg.h>
22#include <plat/gpio-cfg-helpers.h>
23
24static struct s3c_gpio_cfg gpio_cfg = {
25 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
26 .set_pull = s3c_gpio_setpull_updown,
27 .get_pull = s3c_gpio_getpull_updown,
28};
29
30static struct s3c_gpio_cfg gpio_cfg_noint = {
31 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
32 .set_pull = s3c_gpio_setpull_updown,
33 .get_pull = s3c_gpio_getpull_updown,
34};
35
36/*
37 * Following are the gpio banks in v310.
38 *
39 * The 'config' member when left to NULL, is initialized to the default
40 * structure gpio_cfg in the init function below.
41 *
42 * The 'base' member is also initialized in the init function below.
43 * Note: The initialization of 'base' member of s3c_gpio_chip structure
44 * uses the above macro and depends on the banks being listed in order here.
45 */
46static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
47 {
48 .chip = {
49 .base = EXYNOS4_GPA0(0),
50 .ngpio = EXYNOS4_GPIO_A0_NR,
51 .label = "GPA0",
52 },
53 }, {
54 .chip = {
55 .base = EXYNOS4_GPA1(0),
56 .ngpio = EXYNOS4_GPIO_A1_NR,
57 .label = "GPA1",
58 },
59 }, {
60 .chip = {
61 .base = EXYNOS4_GPB(0),
62 .ngpio = EXYNOS4_GPIO_B_NR,
63 .label = "GPB",
64 },
65 }, {
66 .chip = {
67 .base = EXYNOS4_GPC0(0),
68 .ngpio = EXYNOS4_GPIO_C0_NR,
69 .label = "GPC0",
70 },
71 }, {
72 .chip = {
73 .base = EXYNOS4_GPC1(0),
74 .ngpio = EXYNOS4_GPIO_C1_NR,
75 .label = "GPC1",
76 },
77 }, {
78 .chip = {
79 .base = EXYNOS4_GPD0(0),
80 .ngpio = EXYNOS4_GPIO_D0_NR,
81 .label = "GPD0",
82 },
83 }, {
84 .chip = {
85 .base = EXYNOS4_GPD1(0),
86 .ngpio = EXYNOS4_GPIO_D1_NR,
87 .label = "GPD1",
88 },
89 }, {
90 .chip = {
91 .base = EXYNOS4_GPE0(0),
92 .ngpio = EXYNOS4_GPIO_E0_NR,
93 .label = "GPE0",
94 },
95 }, {
96 .chip = {
97 .base = EXYNOS4_GPE1(0),
98 .ngpio = EXYNOS4_GPIO_E1_NR,
99 .label = "GPE1",
100 },
101 }, {
102 .chip = {
103 .base = EXYNOS4_GPE2(0),
104 .ngpio = EXYNOS4_GPIO_E2_NR,
105 .label = "GPE2",
106 },
107 }, {
108 .chip = {
109 .base = EXYNOS4_GPE3(0),
110 .ngpio = EXYNOS4_GPIO_E3_NR,
111 .label = "GPE3",
112 },
113 }, {
114 .chip = {
115 .base = EXYNOS4_GPE4(0),
116 .ngpio = EXYNOS4_GPIO_E4_NR,
117 .label = "GPE4",
118 },
119 }, {
120 .chip = {
121 .base = EXYNOS4_GPF0(0),
122 .ngpio = EXYNOS4_GPIO_F0_NR,
123 .label = "GPF0",
124 },
125 }, {
126 .chip = {
127 .base = EXYNOS4_GPF1(0),
128 .ngpio = EXYNOS4_GPIO_F1_NR,
129 .label = "GPF1",
130 },
131 }, {
132 .chip = {
133 .base = EXYNOS4_GPF2(0),
134 .ngpio = EXYNOS4_GPIO_F2_NR,
135 .label = "GPF2",
136 },
137 }, {
138 .chip = {
139 .base = EXYNOS4_GPF3(0),
140 .ngpio = EXYNOS4_GPIO_F3_NR,
141 .label = "GPF3",
142 },
143 },
144};
145
146static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
147 {
148 .chip = {
149 .base = EXYNOS4_GPJ0(0),
150 .ngpio = EXYNOS4_GPIO_J0_NR,
151 .label = "GPJ0",
152 },
153 }, {
154 .chip = {
155 .base = EXYNOS4_GPJ1(0),
156 .ngpio = EXYNOS4_GPIO_J1_NR,
157 .label = "GPJ1",
158 },
159 }, {
160 .chip = {
161 .base = EXYNOS4_GPK0(0),
162 .ngpio = EXYNOS4_GPIO_K0_NR,
163 .label = "GPK0",
164 },
165 }, {
166 .chip = {
167 .base = EXYNOS4_GPK1(0),
168 .ngpio = EXYNOS4_GPIO_K1_NR,
169 .label = "GPK1",
170 },
171 }, {
172 .chip = {
173 .base = EXYNOS4_GPK2(0),
174 .ngpio = EXYNOS4_GPIO_K2_NR,
175 .label = "GPK2",
176 },
177 }, {
178 .chip = {
179 .base = EXYNOS4_GPK3(0),
180 .ngpio = EXYNOS4_GPIO_K3_NR,
181 .label = "GPK3",
182 },
183 }, {
184 .chip = {
185 .base = EXYNOS4_GPL0(0),
186 .ngpio = EXYNOS4_GPIO_L0_NR,
187 .label = "GPL0",
188 },
189 }, {
190 .chip = {
191 .base = EXYNOS4_GPL1(0),
192 .ngpio = EXYNOS4_GPIO_L1_NR,
193 .label = "GPL1",
194 },
195 }, {
196 .chip = {
197 .base = EXYNOS4_GPL2(0),
198 .ngpio = EXYNOS4_GPIO_L2_NR,
199 .label = "GPL2",
200 },
201 }, {
202 .config = &gpio_cfg_noint,
203 .chip = {
204 .base = EXYNOS4_GPY0(0),
205 .ngpio = EXYNOS4_GPIO_Y0_NR,
206 .label = "GPY0",
207 },
208 }, {
209 .config = &gpio_cfg_noint,
210 .chip = {
211 .base = EXYNOS4_GPY1(0),
212 .ngpio = EXYNOS4_GPIO_Y1_NR,
213 .label = "GPY1",
214 },
215 }, {
216 .config = &gpio_cfg_noint,
217 .chip = {
218 .base = EXYNOS4_GPY2(0),
219 .ngpio = EXYNOS4_GPIO_Y2_NR,
220 .label = "GPY2",
221 },
222 }, {
223 .config = &gpio_cfg_noint,
224 .chip = {
225 .base = EXYNOS4_GPY3(0),
226 .ngpio = EXYNOS4_GPIO_Y3_NR,
227 .label = "GPY3",
228 },
229 }, {
230 .config = &gpio_cfg_noint,
231 .chip = {
232 .base = EXYNOS4_GPY4(0),
233 .ngpio = EXYNOS4_GPIO_Y4_NR,
234 .label = "GPY4",
235 },
236 }, {
237 .config = &gpio_cfg_noint,
238 .chip = {
239 .base = EXYNOS4_GPY5(0),
240 .ngpio = EXYNOS4_GPIO_Y5_NR,
241 .label = "GPY5",
242 },
243 }, {
244 .config = &gpio_cfg_noint,
245 .chip = {
246 .base = EXYNOS4_GPY6(0),
247 .ngpio = EXYNOS4_GPIO_Y6_NR,
248 .label = "GPY6",
249 },
250 }, {
251 .base = (S5P_VA_GPIO2 + 0xC00),
252 .config = &gpio_cfg_noint,
253 .irq_base = IRQ_EINT(0),
254 .chip = {
255 .base = EXYNOS4_GPX0(0),
256 .ngpio = EXYNOS4_GPIO_X0_NR,
257 .label = "GPX0",
258 .to_irq = samsung_gpiolib_to_irq,
259 },
260 }, {
261 .base = (S5P_VA_GPIO2 + 0xC20),
262 .config = &gpio_cfg_noint,
263 .irq_base = IRQ_EINT(8),
264 .chip = {
265 .base = EXYNOS4_GPX1(0),
266 .ngpio = EXYNOS4_GPIO_X1_NR,
267 .label = "GPX1",
268 .to_irq = samsung_gpiolib_to_irq,
269 },
270 }, {
271 .base = (S5P_VA_GPIO2 + 0xC40),
272 .config = &gpio_cfg_noint,
273 .irq_base = IRQ_EINT(16),
274 .chip = {
275 .base = EXYNOS4_GPX2(0),
276 .ngpio = EXYNOS4_GPIO_X2_NR,
277 .label = "GPX2",
278 .to_irq = samsung_gpiolib_to_irq,
279 },
280 }, {
281 .base = (S5P_VA_GPIO2 + 0xC60),
282 .config = &gpio_cfg_noint,
283 .irq_base = IRQ_EINT(24),
284 .chip = {
285 .base = EXYNOS4_GPX3(0),
286 .ngpio = EXYNOS4_GPIO_X3_NR,
287 .label = "GPX3",
288 .to_irq = samsung_gpiolib_to_irq,
289 },
290 },
291};
292
293static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
294 {
295 .chip = {
296 .base = EXYNOS4_GPZ(0),
297 .ngpio = EXYNOS4_GPIO_Z_NR,
298 .label = "GPZ",
299 },
300 },
301};
302
303static __init int exynos4_gpiolib_init(void)
304{
305 struct s3c_gpio_chip *chip;
306 int i;
307 int group = 0;
308 int nr_chips;
309
310 /* GPIO part 1 */
311
312 chip = exynos4_gpio_part1_4bit;
313 nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
314
315 for (i = 0; i < nr_chips; i++, chip++) {
316 if (chip->config == NULL) {
317 chip->config = &gpio_cfg;
318 /* Assign the GPIO interrupt group */
319 chip->group = group++;
320 }
321 if (chip->base == NULL)
322 chip->base = S5P_VA_GPIO1 + (i) * 0x20;
323 }
324
325 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
326
327 /* GPIO part 2 */
328
329 chip = exynos4_gpio_part2_4bit;
330 nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
331
332 for (i = 0; i < nr_chips; i++, chip++) {
333 if (chip->config == NULL) {
334 chip->config = &gpio_cfg;
335 /* Assign the GPIO interrupt group */
336 chip->group = group++;
337 }
338 if (chip->base == NULL)
339 chip->base = S5P_VA_GPIO2 + (i) * 0x20;
340 }
341
342 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
343
344 /* GPIO part 3 */
345
346 chip = exynos4_gpio_part3_4bit;
347 nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
348
349 for (i = 0; i < nr_chips; i++, chip++) {
350 if (chip->config == NULL) {
351 chip->config = &gpio_cfg;
352 /* Assign the GPIO interrupt group */
353 chip->group = group++;
354 }
355 if (chip->base == NULL)
356 chip->base = S5P_VA_GPIO3 + (i) * 0x20;
357 }
358
359 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
360 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
361 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
362
363 return 0;
364}
365core_initcall(exynos4_gpiolib_init);
diff --git a/drivers/gpio/gpio-nomadik.c b/drivers/gpio/gpio-nomadik.c
new file mode 100644
index 000000000000..4961ef9bc153
--- /dev/null
+++ b/drivers/gpio/gpio-nomadik.c
@@ -0,0 +1,1069 @@
1/*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/device.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20#include <linux/gpio.h>
21#include <linux/spinlock.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/slab.h>
25
26#include <asm/mach/irq.h>
27
28#include <plat/pincfg.h>
29#include <mach/hardware.h>
30#include <mach/gpio.h>
31
32/*
33 * The GPIO module in the Nomadik family of Systems-on-Chip is an
34 * AMBA device, managing 32 pins and alternate functions. The logic block
35 * is currently used in the Nomadik and ux500.
36 *
37 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
38 */
39
40#define NMK_GPIO_PER_CHIP 32
41
42struct nmk_gpio_chip {
43 struct gpio_chip chip;
44 void __iomem *addr;
45 struct clk *clk;
46 unsigned int bank;
47 unsigned int parent_irq;
48 int secondary_parent_irq;
49 u32 (*get_secondary_status)(unsigned int bank);
50 void (*set_ioforce)(bool enable);
51 spinlock_t lock;
52 /* Keep track of configured edges */
53 u32 edge_rising;
54 u32 edge_falling;
55 u32 real_wake;
56 u32 rwimsc;
57 u32 fwimsc;
58 u32 slpm;
59 u32 enabled;
60 u32 pull_up;
61};
62
63static struct nmk_gpio_chip *
64nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
65
66static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
67
68#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
69
70static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
71 unsigned offset, int gpio_mode)
72{
73 u32 bit = 1 << offset;
74 u32 afunc, bfunc;
75
76 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
77 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
78 if (gpio_mode & NMK_GPIO_ALT_A)
79 afunc |= bit;
80 if (gpio_mode & NMK_GPIO_ALT_B)
81 bfunc |= bit;
82 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
83 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
84}
85
86static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
87 unsigned offset, enum nmk_gpio_slpm mode)
88{
89 u32 bit = 1 << offset;
90 u32 slpm;
91
92 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
93 if (mode == NMK_GPIO_SLPM_NOCHANGE)
94 slpm |= bit;
95 else
96 slpm &= ~bit;
97 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
98}
99
100static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
101 unsigned offset, enum nmk_gpio_pull pull)
102{
103 u32 bit = 1 << offset;
104 u32 pdis;
105
106 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
107 if (pull == NMK_GPIO_PULL_NONE) {
108 pdis |= bit;
109 nmk_chip->pull_up &= ~bit;
110 } else {
111 pdis &= ~bit;
112 }
113
114 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
115
116 if (pull == NMK_GPIO_PULL_UP) {
117 nmk_chip->pull_up |= bit;
118 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
119 } else if (pull == NMK_GPIO_PULL_DOWN) {
120 nmk_chip->pull_up &= ~bit;
121 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
122 }
123}
124
125static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
126 unsigned offset)
127{
128 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
129}
130
131static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
132 unsigned offset, int val)
133{
134 if (val)
135 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
136 else
137 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
138}
139
140static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
141 unsigned offset, int val)
142{
143 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
144 __nmk_gpio_set_output(nmk_chip, offset, val);
145}
146
147static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
148 unsigned offset, int gpio_mode,
149 bool glitch)
150{
151 u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
152 u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
153
154 if (glitch && nmk_chip->set_ioforce) {
155 u32 bit = BIT(offset);
156
157 /* Prevent spurious wakeups */
158 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
159 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
160
161 nmk_chip->set_ioforce(true);
162 }
163
164 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
165
166 if (glitch && nmk_chip->set_ioforce) {
167 nmk_chip->set_ioforce(false);
168
169 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
170 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
171 }
172}
173
174static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
175 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
176{
177 static const char *afnames[] = {
178 [NMK_GPIO_ALT_GPIO] = "GPIO",
179 [NMK_GPIO_ALT_A] = "A",
180 [NMK_GPIO_ALT_B] = "B",
181 [NMK_GPIO_ALT_C] = "C"
182 };
183 static const char *pullnames[] = {
184 [NMK_GPIO_PULL_NONE] = "none",
185 [NMK_GPIO_PULL_UP] = "up",
186 [NMK_GPIO_PULL_DOWN] = "down",
187 [3] /* illegal */ = "??"
188 };
189 static const char *slpmnames[] = {
190 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
191 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
192 };
193
194 int pin = PIN_NUM(cfg);
195 int pull = PIN_PULL(cfg);
196 int af = PIN_ALT(cfg);
197 int slpm = PIN_SLPM(cfg);
198 int output = PIN_DIR(cfg);
199 int val = PIN_VAL(cfg);
200 bool glitch = af == NMK_GPIO_ALT_C;
201
202 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
203 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
204 output ? "output " : "input",
205 output ? (val ? "high" : "low") : "");
206
207 if (sleep) {
208 int slpm_pull = PIN_SLPM_PULL(cfg);
209 int slpm_output = PIN_SLPM_DIR(cfg);
210 int slpm_val = PIN_SLPM_VAL(cfg);
211
212 af = NMK_GPIO_ALT_GPIO;
213
214 /*
215 * The SLPM_* values are normal values + 1 to allow zero to
216 * mean "same as normal".
217 */
218 if (slpm_pull)
219 pull = slpm_pull - 1;
220 if (slpm_output)
221 output = slpm_output - 1;
222 if (slpm_val)
223 val = slpm_val - 1;
224
225 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
226 pin,
227 slpm_pull ? pullnames[pull] : "same",
228 slpm_output ? (output ? "output" : "input") : "same",
229 slpm_val ? (val ? "high" : "low") : "same");
230 }
231
232 if (output)
233 __nmk_gpio_make_output(nmk_chip, offset, val);
234 else {
235 __nmk_gpio_make_input(nmk_chip, offset);
236 __nmk_gpio_set_pull(nmk_chip, offset, pull);
237 }
238
239 /*
240 * If we've backed up the SLPM registers (glitch workaround), modify
241 * the backups since they will be restored.
242 */
243 if (slpmregs) {
244 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
245 slpmregs[nmk_chip->bank] |= BIT(offset);
246 else
247 slpmregs[nmk_chip->bank] &= ~BIT(offset);
248 } else
249 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
250
251 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
252}
253
254/*
255 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
256 * - Save SLPM registers
257 * - Set SLPM=0 for the IOs you want to switch and others to 1
258 * - Configure the GPIO registers for the IOs that are being switched
259 * - Set IOFORCE=1
260 * - Modify the AFLSA/B registers for the IOs that are being switched
261 * - Set IOFORCE=0
262 * - Restore SLPM registers
263 * - Any spurious wake up event during switch sequence to be ignored and
264 * cleared
265 */
266static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
267{
268 int i;
269
270 for (i = 0; i < NUM_BANKS; i++) {
271 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
272 unsigned int temp = slpm[i];
273
274 if (!chip)
275 break;
276
277 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
278 writel(temp, chip->addr + NMK_GPIO_SLPC);
279 }
280}
281
282static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
283{
284 int i;
285
286 for (i = 0; i < NUM_BANKS; i++) {
287 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
288
289 if (!chip)
290 break;
291
292 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
293 }
294}
295
296static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
297{
298 static unsigned int slpm[NUM_BANKS];
299 unsigned long flags;
300 bool glitch = false;
301 int ret = 0;
302 int i;
303
304 for (i = 0; i < num; i++) {
305 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
306 glitch = true;
307 break;
308 }
309 }
310
311 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
312
313 if (glitch) {
314 memset(slpm, 0xff, sizeof(slpm));
315
316 for (i = 0; i < num; i++) {
317 int pin = PIN_NUM(cfgs[i]);
318 int offset = pin % NMK_GPIO_PER_CHIP;
319
320 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
321 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
322 }
323
324 nmk_gpio_glitch_slpm_init(slpm);
325 }
326
327 for (i = 0; i < num; i++) {
328 struct nmk_gpio_chip *nmk_chip;
329 int pin = PIN_NUM(cfgs[i]);
330
331 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
332 if (!nmk_chip) {
333 ret = -EINVAL;
334 break;
335 }
336
337 spin_lock(&nmk_chip->lock);
338 __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base,
339 cfgs[i], sleep, glitch ? slpm : NULL);
340 spin_unlock(&nmk_chip->lock);
341 }
342
343 if (glitch)
344 nmk_gpio_glitch_slpm_restore(slpm);
345
346 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
347
348 return ret;
349}
350
351/**
352 * nmk_config_pin - configure a pin's mux attributes
353 * @cfg: pin confguration
354 *
355 * Configures a pin's mode (alternate function or GPIO), its pull up status,
356 * and its sleep mode based on the specified configuration. The @cfg is
357 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
358 * are constructed using, and can be further enhanced with, the macros in
359 * plat/pincfg.h.
360 *
361 * If a pin's mode is set to GPIO, it is configured as an input to avoid
362 * side-effects. The gpio can be manipulated later using standard GPIO API
363 * calls.
364 */
365int nmk_config_pin(pin_cfg_t cfg, bool sleep)
366{
367 return __nmk_config_pins(&cfg, 1, sleep);
368}
369EXPORT_SYMBOL(nmk_config_pin);
370
371/**
372 * nmk_config_pins - configure several pins at once
373 * @cfgs: array of pin configurations
374 * @num: number of elments in the array
375 *
376 * Configures several pins using nmk_config_pin(). Refer to that function for
377 * further information.
378 */
379int nmk_config_pins(pin_cfg_t *cfgs, int num)
380{
381 return __nmk_config_pins(cfgs, num, false);
382}
383EXPORT_SYMBOL(nmk_config_pins);
384
385int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
386{
387 return __nmk_config_pins(cfgs, num, true);
388}
389EXPORT_SYMBOL(nmk_config_pins_sleep);
390
391/**
392 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
393 * @gpio: pin number
394 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
395 *
396 * Sets the sleep mode of a pin. If @mode is NMK_GPIO_SLPM_INPUT, the pin is
397 * changed to an input (with pullup/down enabled) in sleep and deep sleep. If
398 * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was
399 * configured even when in sleep and deep sleep.
400 *
401 * On DB8500v2 onwards, this setting loses the previous meaning and instead
402 * indicates if wakeup detection is enabled on the pin. Note that
403 * enable_irq_wake() will automatically enable wakeup detection.
404 */
405int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
406{
407 struct nmk_gpio_chip *nmk_chip;
408 unsigned long flags;
409
410 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
411 if (!nmk_chip)
412 return -EINVAL;
413
414 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
415 spin_lock(&nmk_chip->lock);
416
417 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
418
419 spin_unlock(&nmk_chip->lock);
420 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
421
422 return 0;
423}
424
425/**
426 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
427 * @gpio: pin number
428 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
429 *
430 * Enables/disables pull up/down on a specified pin. This only takes effect if
431 * the pin is configured as an input (either explicitly or by the alternate
432 * function).
433 *
434 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
435 * configured as an input. Otherwise, due to the way the controller registers
436 * work, this function will change the value output on the pin.
437 */
438int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
439{
440 struct nmk_gpio_chip *nmk_chip;
441 unsigned long flags;
442
443 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
444 if (!nmk_chip)
445 return -EINVAL;
446
447 spin_lock_irqsave(&nmk_chip->lock, flags);
448 __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull);
449 spin_unlock_irqrestore(&nmk_chip->lock, flags);
450
451 return 0;
452}
453
454/* Mode functions */
455/**
456 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
457 * @gpio: pin number
458 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
459 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
460 *
461 * Sets the mode of the specified pin to one of the alternate functions or
462 * plain GPIO.
463 */
464int nmk_gpio_set_mode(int gpio, int gpio_mode)
465{
466 struct nmk_gpio_chip *nmk_chip;
467 unsigned long flags;
468
469 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
470 if (!nmk_chip)
471 return -EINVAL;
472
473 spin_lock_irqsave(&nmk_chip->lock, flags);
474 __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode);
475 spin_unlock_irqrestore(&nmk_chip->lock, flags);
476
477 return 0;
478}
479EXPORT_SYMBOL(nmk_gpio_set_mode);
480
481int nmk_gpio_get_mode(int gpio)
482{
483 struct nmk_gpio_chip *nmk_chip;
484 u32 afunc, bfunc, bit;
485
486 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
487 if (!nmk_chip)
488 return -EINVAL;
489
490 bit = 1 << (gpio - nmk_chip->chip.base);
491
492 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
493 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
494
495 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
496}
497EXPORT_SYMBOL(nmk_gpio_get_mode);
498
499
500/* IRQ functions */
501static inline int nmk_gpio_get_bitmask(int gpio)
502{
503 return 1 << (gpio % 32);
504}
505
506static void nmk_gpio_irq_ack(struct irq_data *d)
507{
508 int gpio;
509 struct nmk_gpio_chip *nmk_chip;
510
511 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
512 nmk_chip = irq_data_get_irq_chip_data(d);
513 if (!nmk_chip)
514 return;
515 writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
516}
517
518enum nmk_gpio_irq_type {
519 NORMAL,
520 WAKE,
521};
522
523static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
524 int gpio, enum nmk_gpio_irq_type which,
525 bool enable)
526{
527 u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
528 u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
529 u32 bitmask = nmk_gpio_get_bitmask(gpio);
530 u32 reg;
531
532 /* we must individually set/clear the two edges */
533 if (nmk_chip->edge_rising & bitmask) {
534 reg = readl(nmk_chip->addr + rimsc);
535 if (enable)
536 reg |= bitmask;
537 else
538 reg &= ~bitmask;
539 writel(reg, nmk_chip->addr + rimsc);
540 }
541 if (nmk_chip->edge_falling & bitmask) {
542 reg = readl(nmk_chip->addr + fimsc);
543 if (enable)
544 reg |= bitmask;
545 else
546 reg &= ~bitmask;
547 writel(reg, nmk_chip->addr + fimsc);
548 }
549}
550
551static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
552 int gpio, bool on)
553{
554 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
555}
556
557static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
558{
559 int gpio;
560 struct nmk_gpio_chip *nmk_chip;
561 unsigned long flags;
562 u32 bitmask;
563
564 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
565 nmk_chip = irq_data_get_irq_chip_data(d);
566 bitmask = nmk_gpio_get_bitmask(gpio);
567 if (!nmk_chip)
568 return -EINVAL;
569
570 if (enable)
571 nmk_chip->enabled |= bitmask;
572 else
573 nmk_chip->enabled &= ~bitmask;
574
575 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
576 spin_lock(&nmk_chip->lock);
577
578 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable);
579
580 if (!(nmk_chip->real_wake & bitmask))
581 __nmk_gpio_set_wake(nmk_chip, gpio, enable);
582
583 spin_unlock(&nmk_chip->lock);
584 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
585
586 return 0;
587}
588
589static void nmk_gpio_irq_mask(struct irq_data *d)
590{
591 nmk_gpio_irq_maskunmask(d, false);
592}
593
594static void nmk_gpio_irq_unmask(struct irq_data *d)
595{
596 nmk_gpio_irq_maskunmask(d, true);
597}
598
599static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
600{
601 struct nmk_gpio_chip *nmk_chip;
602 unsigned long flags;
603 u32 bitmask;
604 int gpio;
605
606 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
607 nmk_chip = irq_data_get_irq_chip_data(d);
608 if (!nmk_chip)
609 return -EINVAL;
610 bitmask = nmk_gpio_get_bitmask(gpio);
611
612 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
613 spin_lock(&nmk_chip->lock);
614
615 if (!(nmk_chip->enabled & bitmask))
616 __nmk_gpio_set_wake(nmk_chip, gpio, on);
617
618 if (on)
619 nmk_chip->real_wake |= bitmask;
620 else
621 nmk_chip->real_wake &= ~bitmask;
622
623 spin_unlock(&nmk_chip->lock);
624 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
625
626 return 0;
627}
628
629static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
630{
631 bool enabled, wake = irqd_is_wakeup_set(d);
632 int gpio;
633 struct nmk_gpio_chip *nmk_chip;
634 unsigned long flags;
635 u32 bitmask;
636
637 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
638 nmk_chip = irq_data_get_irq_chip_data(d);
639 bitmask = nmk_gpio_get_bitmask(gpio);
640 if (!nmk_chip)
641 return -EINVAL;
642
643 if (type & IRQ_TYPE_LEVEL_HIGH)
644 return -EINVAL;
645 if (type & IRQ_TYPE_LEVEL_LOW)
646 return -EINVAL;
647
648 enabled = nmk_chip->enabled & bitmask;
649
650 spin_lock_irqsave(&nmk_chip->lock, flags);
651
652 if (enabled)
653 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
654
655 if (enabled || wake)
656 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
657
658 nmk_chip->edge_rising &= ~bitmask;
659 if (type & IRQ_TYPE_EDGE_RISING)
660 nmk_chip->edge_rising |= bitmask;
661
662 nmk_chip->edge_falling &= ~bitmask;
663 if (type & IRQ_TYPE_EDGE_FALLING)
664 nmk_chip->edge_falling |= bitmask;
665
666 if (enabled)
667 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
668
669 if (enabled || wake)
670 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
671
672 spin_unlock_irqrestore(&nmk_chip->lock, flags);
673
674 return 0;
675}
676
677static struct irq_chip nmk_gpio_irq_chip = {
678 .name = "Nomadik-GPIO",
679 .irq_ack = nmk_gpio_irq_ack,
680 .irq_mask = nmk_gpio_irq_mask,
681 .irq_unmask = nmk_gpio_irq_unmask,
682 .irq_set_type = nmk_gpio_irq_set_type,
683 .irq_set_wake = nmk_gpio_irq_set_wake,
684};
685
686static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
687 u32 status)
688{
689 struct nmk_gpio_chip *nmk_chip;
690 struct irq_chip *host_chip = irq_get_chip(irq);
691 unsigned int first_irq;
692
693 chained_irq_enter(host_chip, desc);
694
695 nmk_chip = irq_get_handler_data(irq);
696 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
697 while (status) {
698 int bit = __ffs(status);
699
700 generic_handle_irq(first_irq + bit);
701 status &= ~BIT(bit);
702 }
703
704 chained_irq_exit(host_chip, desc);
705}
706
707static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
708{
709 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
710 u32 status = readl(nmk_chip->addr + NMK_GPIO_IS);
711
712 __nmk_gpio_irq_handler(irq, desc, status);
713}
714
715static void nmk_gpio_secondary_irq_handler(unsigned int irq,
716 struct irq_desc *desc)
717{
718 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
719 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
720
721 __nmk_gpio_irq_handler(irq, desc, status);
722}
723
724static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
725{
726 unsigned int first_irq;
727 int i;
728
729 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
730 for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
731 irq_set_chip_and_handler(i, &nmk_gpio_irq_chip,
732 handle_edge_irq);
733 set_irq_flags(i, IRQF_VALID);
734 irq_set_chip_data(i, nmk_chip);
735 irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
736 }
737
738 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
739 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
740
741 if (nmk_chip->secondary_parent_irq >= 0) {
742 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
743 nmk_gpio_secondary_irq_handler);
744 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
745 }
746
747 return 0;
748}
749
750/* I/O Functions */
751static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
752{
753 struct nmk_gpio_chip *nmk_chip =
754 container_of(chip, struct nmk_gpio_chip, chip);
755
756 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
757 return 0;
758}
759
760static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
761{
762 struct nmk_gpio_chip *nmk_chip =
763 container_of(chip, struct nmk_gpio_chip, chip);
764 u32 bit = 1 << offset;
765
766 return (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
767}
768
769static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
770 int val)
771{
772 struct nmk_gpio_chip *nmk_chip =
773 container_of(chip, struct nmk_gpio_chip, chip);
774
775 __nmk_gpio_set_output(nmk_chip, offset, val);
776}
777
778static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
779 int val)
780{
781 struct nmk_gpio_chip *nmk_chip =
782 container_of(chip, struct nmk_gpio_chip, chip);
783
784 __nmk_gpio_make_output(nmk_chip, offset, val);
785
786 return 0;
787}
788
789static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
790{
791 struct nmk_gpio_chip *nmk_chip =
792 container_of(chip, struct nmk_gpio_chip, chip);
793
794 return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
795}
796
797#ifdef CONFIG_DEBUG_FS
798
799#include <linux/seq_file.h>
800
801static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
802{
803 int mode;
804 unsigned i;
805 unsigned gpio = chip->base;
806 int is_out;
807 struct nmk_gpio_chip *nmk_chip =
808 container_of(chip, struct nmk_gpio_chip, chip);
809 const char *modes[] = {
810 [NMK_GPIO_ALT_GPIO] = "gpio",
811 [NMK_GPIO_ALT_A] = "altA",
812 [NMK_GPIO_ALT_B] = "altB",
813 [NMK_GPIO_ALT_C] = "altC",
814 };
815
816 for (i = 0; i < chip->ngpio; i++, gpio++) {
817 const char *label = gpiochip_is_requested(chip, i);
818 bool pull;
819 u32 bit = 1 << i;
820
821 is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit;
822 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
823 mode = nmk_gpio_get_mode(gpio);
824 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
825 gpio, label ?: "(none)",
826 is_out ? "out" : "in ",
827 chip->get
828 ? (chip->get(chip, i) ? "hi" : "lo")
829 : "? ",
830 (mode < 0) ? "unknown" : modes[mode],
831 pull ? "pull" : "none");
832
833 if (label && !is_out) {
834 int irq = gpio_to_irq(gpio);
835 struct irq_desc *desc = irq_to_desc(irq);
836
837 /* This races with request_irq(), set_irq_type(),
838 * and set_irq_wake() ... but those are "rare".
839 */
840 if (irq >= 0 && desc->action) {
841 char *trigger;
842 u32 bitmask = nmk_gpio_get_bitmask(gpio);
843
844 if (nmk_chip->edge_rising & bitmask)
845 trigger = "edge-rising";
846 else if (nmk_chip->edge_falling & bitmask)
847 trigger = "edge-falling";
848 else
849 trigger = "edge-undefined";
850
851 seq_printf(s, " irq-%d %s%s",
852 irq, trigger,
853 irqd_is_wakeup_set(&desc->irq_data)
854 ? " wakeup" : "");
855 }
856 }
857
858 seq_printf(s, "\n");
859 }
860}
861
862#else
863#define nmk_gpio_dbg_show NULL
864#endif
865
866/* This structure is replicated for each GPIO block allocated at probe time */
867static struct gpio_chip nmk_gpio_template = {
868 .direction_input = nmk_gpio_make_input,
869 .get = nmk_gpio_get_input,
870 .direction_output = nmk_gpio_make_output,
871 .set = nmk_gpio_set_output,
872 .to_irq = nmk_gpio_to_irq,
873 .dbg_show = nmk_gpio_dbg_show,
874 .can_sleep = 0,
875};
876
877/*
878 * Called from the suspend/resume path to only keep the real wakeup interrupts
879 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
880 * and not the rest of the interrupts which we needed to have as wakeups for
881 * cpuidle.
882 *
883 * PM ops are not used since this needs to be done at the end, after all the
884 * other drivers are done with their suspend callbacks.
885 */
886void nmk_gpio_wakeups_suspend(void)
887{
888 int i;
889
890 for (i = 0; i < NUM_BANKS; i++) {
891 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
892
893 if (!chip)
894 break;
895
896 chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC);
897 chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC);
898
899 writel(chip->rwimsc & chip->real_wake,
900 chip->addr + NMK_GPIO_RWIMSC);
901 writel(chip->fwimsc & chip->real_wake,
902 chip->addr + NMK_GPIO_FWIMSC);
903
904 if (cpu_is_u8500v2()) {
905 chip->slpm = readl(chip->addr + NMK_GPIO_SLPC);
906
907 /* 0 -> wakeup enable */
908 writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC);
909 }
910 }
911}
912
913void nmk_gpio_wakeups_resume(void)
914{
915 int i;
916
917 for (i = 0; i < NUM_BANKS; i++) {
918 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
919
920 if (!chip)
921 break;
922
923 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
924 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
925
926 if (cpu_is_u8500v2())
927 writel(chip->slpm, chip->addr + NMK_GPIO_SLPC);
928 }
929}
930
931/*
932 * Read the pull up/pull down status.
933 * A bit set in 'pull_up' means that pull up
934 * is selected if pull is enabled in PDIS register.
935 * Note: only pull up/down set via this driver can
936 * be detected due to HW limitations.
937 */
938void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
939{
940 if (gpio_bank < NUM_BANKS) {
941 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
942
943 if (!chip)
944 return;
945
946 *pull_up = chip->pull_up;
947 }
948}
949
950static int __devinit nmk_gpio_probe(struct platform_device *dev)
951{
952 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
953 struct nmk_gpio_chip *nmk_chip;
954 struct gpio_chip *chip;
955 struct resource *res;
956 struct clk *clk;
957 int secondary_irq;
958 int irq;
959 int ret;
960
961 if (!pdata)
962 return -ENODEV;
963
964 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
965 if (!res) {
966 ret = -ENOENT;
967 goto out;
968 }
969
970 irq = platform_get_irq(dev, 0);
971 if (irq < 0) {
972 ret = irq;
973 goto out;
974 }
975
976 secondary_irq = platform_get_irq(dev, 1);
977 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
978 ret = -EINVAL;
979 goto out;
980 }
981
982 if (request_mem_region(res->start, resource_size(res),
983 dev_name(&dev->dev)) == NULL) {
984 ret = -EBUSY;
985 goto out;
986 }
987
988 clk = clk_get(&dev->dev, NULL);
989 if (IS_ERR(clk)) {
990 ret = PTR_ERR(clk);
991 goto out_release;
992 }
993
994 clk_enable(clk);
995
996 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
997 if (!nmk_chip) {
998 ret = -ENOMEM;
999 goto out_clk;
1000 }
1001 /*
1002 * The virt address in nmk_chip->addr is in the nomadik register space,
1003 * so we can simply convert the resource address, without remapping
1004 */
1005 nmk_chip->bank = dev->id;
1006 nmk_chip->clk = clk;
1007 nmk_chip->addr = io_p2v(res->start);
1008 nmk_chip->chip = nmk_gpio_template;
1009 nmk_chip->parent_irq = irq;
1010 nmk_chip->secondary_parent_irq = secondary_irq;
1011 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1012 nmk_chip->set_ioforce = pdata->set_ioforce;
1013 spin_lock_init(&nmk_chip->lock);
1014
1015 chip = &nmk_chip->chip;
1016 chip->base = pdata->first_gpio;
1017 chip->ngpio = pdata->num_gpio;
1018 chip->label = pdata->name ?: dev_name(&dev->dev);
1019 chip->dev = &dev->dev;
1020 chip->owner = THIS_MODULE;
1021
1022 ret = gpiochip_add(&nmk_chip->chip);
1023 if (ret)
1024 goto out_free;
1025
1026 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1027
1028 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1029 platform_set_drvdata(dev, nmk_chip);
1030
1031 nmk_gpio_init_irq(nmk_chip);
1032
1033 dev_info(&dev->dev, "Bits %i-%i at address %p\n",
1034 nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr);
1035 return 0;
1036
1037out_free:
1038 kfree(nmk_chip);
1039out_clk:
1040 clk_disable(clk);
1041 clk_put(clk);
1042out_release:
1043 release_mem_region(res->start, resource_size(res));
1044out:
1045 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1046 pdata->first_gpio, pdata->first_gpio+31);
1047 return ret;
1048}
1049
1050static struct platform_driver nmk_gpio_driver = {
1051 .driver = {
1052 .owner = THIS_MODULE,
1053 .name = "gpio",
1054 },
1055 .probe = nmk_gpio_probe,
1056};
1057
1058static int __init nmk_gpio_init(void)
1059{
1060 return platform_driver_register(&nmk_gpio_driver);
1061}
1062
1063core_initcall(nmk_gpio_init);
1064
1065MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1066MODULE_DESCRIPTION("Nomadik GPIO Driver");
1067MODULE_LICENSE("GPL");
1068
1069
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
new file mode 100644
index 000000000000..6c51191da567
--- /dev/null
+++ b/drivers/gpio/gpio-omap.c
@@ -0,0 +1,2007 @@
1/*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/syscore_ops.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
24
25#include <mach/hardware.h>
26#include <asm/irq.h>
27#include <mach/irqs.h>
28#include <mach/gpio.h>
29#include <asm/mach/irq.h>
30
31struct gpio_bank {
32 unsigned long pbase;
33 void __iomem *base;
34 u16 irq;
35 u16 virtual_irq_start;
36 int method;
37#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
38 u32 suspend_wakeup;
39 u32 saved_wakeup;
40#endif
41 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios;
43
44 u32 saved_datain;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
47 u32 level_mask;
48 u32 toggle_mask;
49 spinlock_t lock;
50 struct gpio_chip chip;
51 struct clk *dbck;
52 u32 mod_usage;
53 u32 dbck_enable_mask;
54 struct device *dev;
55 bool dbck_flag;
56 int stride;
57};
58
59#ifdef CONFIG_ARCH_OMAP3
60struct omap3_gpio_regs {
61 u32 irqenable1;
62 u32 irqenable2;
63 u32 wake_en;
64 u32 ctrl;
65 u32 oe;
66 u32 leveldetect0;
67 u32 leveldetect1;
68 u32 risingdetect;
69 u32 fallingdetect;
70 u32 dataout;
71};
72
73static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
74#endif
75
76/*
77 * TODO: Cleanup gpio_bank usage as it is having information
78 * related to all instances of the device
79 */
80static struct gpio_bank *gpio_bank;
81
82static int bank_width;
83
84/* TODO: Analyze removing gpio_bank_count usage from driver code */
85int gpio_bank_count;
86
87static inline struct gpio_bank *get_gpio_bank(int gpio)
88{
89 if (cpu_is_omap15xx()) {
90 if (OMAP_GPIO_IS_MPUIO(gpio))
91 return &gpio_bank[0];
92 return &gpio_bank[1];
93 }
94 if (cpu_is_omap16xx()) {
95 if (OMAP_GPIO_IS_MPUIO(gpio))
96 return &gpio_bank[0];
97 return &gpio_bank[1 + (gpio >> 4)];
98 }
99 if (cpu_is_omap7xx()) {
100 if (OMAP_GPIO_IS_MPUIO(gpio))
101 return &gpio_bank[0];
102 return &gpio_bank[1 + (gpio >> 5)];
103 }
104 if (cpu_is_omap24xx())
105 return &gpio_bank[gpio >> 5];
106 if (cpu_is_omap34xx() || cpu_is_omap44xx())
107 return &gpio_bank[gpio >> 5];
108 BUG();
109 return NULL;
110}
111
112static inline int get_gpio_index(int gpio)
113{
114 if (cpu_is_omap7xx())
115 return gpio & 0x1f;
116 if (cpu_is_omap24xx())
117 return gpio & 0x1f;
118 if (cpu_is_omap34xx() || cpu_is_omap44xx())
119 return gpio & 0x1f;
120 return gpio & 0x0f;
121}
122
123static inline int gpio_valid(int gpio)
124{
125 if (gpio < 0)
126 return -1;
127 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
128 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
129 return -1;
130 return 0;
131 }
132 if (cpu_is_omap15xx() && gpio < 16)
133 return 0;
134 if ((cpu_is_omap16xx()) && gpio < 64)
135 return 0;
136 if (cpu_is_omap7xx() && gpio < 192)
137 return 0;
138 if (cpu_is_omap2420() && gpio < 128)
139 return 0;
140 if (cpu_is_omap2430() && gpio < 160)
141 return 0;
142 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
143 return 0;
144 return -1;
145}
146
147static int check_gpio(int gpio)
148{
149 if (unlikely(gpio_valid(gpio) < 0)) {
150 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
151 dump_stack();
152 return -1;
153 }
154 return 0;
155}
156
157static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
158{
159 void __iomem *reg = bank->base;
160 u32 l;
161
162 switch (bank->method) {
163#ifdef CONFIG_ARCH_OMAP1
164 case METHOD_MPUIO:
165 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
166 break;
167#endif
168#ifdef CONFIG_ARCH_OMAP15XX
169 case METHOD_GPIO_1510:
170 reg += OMAP1510_GPIO_DIR_CONTROL;
171 break;
172#endif
173#ifdef CONFIG_ARCH_OMAP16XX
174 case METHOD_GPIO_1610:
175 reg += OMAP1610_GPIO_DIRECTION;
176 break;
177#endif
178#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
179 case METHOD_GPIO_7XX:
180 reg += OMAP7XX_GPIO_DIR_CONTROL;
181 break;
182#endif
183#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
184 case METHOD_GPIO_24XX:
185 reg += OMAP24XX_GPIO_OE;
186 break;
187#endif
188#if defined(CONFIG_ARCH_OMAP4)
189 case METHOD_GPIO_44XX:
190 reg += OMAP4_GPIO_OE;
191 break;
192#endif
193 default:
194 WARN_ON(1);
195 return;
196 }
197 l = __raw_readl(reg);
198 if (is_input)
199 l |= 1 << gpio;
200 else
201 l &= ~(1 << gpio);
202 __raw_writel(l, reg);
203}
204
205static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
206{
207 void __iomem *reg = bank->base;
208 u32 l = 0;
209
210 switch (bank->method) {
211#ifdef CONFIG_ARCH_OMAP1
212 case METHOD_MPUIO:
213 reg += OMAP_MPUIO_OUTPUT / bank->stride;
214 l = __raw_readl(reg);
215 if (enable)
216 l |= 1 << gpio;
217 else
218 l &= ~(1 << gpio);
219 break;
220#endif
221#ifdef CONFIG_ARCH_OMAP15XX
222 case METHOD_GPIO_1510:
223 reg += OMAP1510_GPIO_DATA_OUTPUT;
224 l = __raw_readl(reg);
225 if (enable)
226 l |= 1 << gpio;
227 else
228 l &= ~(1 << gpio);
229 break;
230#endif
231#ifdef CONFIG_ARCH_OMAP16XX
232 case METHOD_GPIO_1610:
233 if (enable)
234 reg += OMAP1610_GPIO_SET_DATAOUT;
235 else
236 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
237 l = 1 << gpio;
238 break;
239#endif
240#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
241 case METHOD_GPIO_7XX:
242 reg += OMAP7XX_GPIO_DATA_OUTPUT;
243 l = __raw_readl(reg);
244 if (enable)
245 l |= 1 << gpio;
246 else
247 l &= ~(1 << gpio);
248 break;
249#endif
250#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
251 case METHOD_GPIO_24XX:
252 if (enable)
253 reg += OMAP24XX_GPIO_SETDATAOUT;
254 else
255 reg += OMAP24XX_GPIO_CLEARDATAOUT;
256 l = 1 << gpio;
257 break;
258#endif
259#ifdef CONFIG_ARCH_OMAP4
260 case METHOD_GPIO_44XX:
261 if (enable)
262 reg += OMAP4_GPIO_SETDATAOUT;
263 else
264 reg += OMAP4_GPIO_CLEARDATAOUT;
265 l = 1 << gpio;
266 break;
267#endif
268 default:
269 WARN_ON(1);
270 return;
271 }
272 __raw_writel(l, reg);
273}
274
275static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
276{
277 void __iomem *reg;
278
279 if (check_gpio(gpio) < 0)
280 return -EINVAL;
281 reg = bank->base;
282 switch (bank->method) {
283#ifdef CONFIG_ARCH_OMAP1
284 case METHOD_MPUIO:
285 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
286 break;
287#endif
288#ifdef CONFIG_ARCH_OMAP15XX
289 case METHOD_GPIO_1510:
290 reg += OMAP1510_GPIO_DATA_INPUT;
291 break;
292#endif
293#ifdef CONFIG_ARCH_OMAP16XX
294 case METHOD_GPIO_1610:
295 reg += OMAP1610_GPIO_DATAIN;
296 break;
297#endif
298#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
299 case METHOD_GPIO_7XX:
300 reg += OMAP7XX_GPIO_DATA_INPUT;
301 break;
302#endif
303#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
304 case METHOD_GPIO_24XX:
305 reg += OMAP24XX_GPIO_DATAIN;
306 break;
307#endif
308#ifdef CONFIG_ARCH_OMAP4
309 case METHOD_GPIO_44XX:
310 reg += OMAP4_GPIO_DATAIN;
311 break;
312#endif
313 default:
314 return -EINVAL;
315 }
316 return (__raw_readl(reg)
317 & (1 << get_gpio_index(gpio))) != 0;
318}
319
320static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
321{
322 void __iomem *reg;
323
324 if (check_gpio(gpio) < 0)
325 return -EINVAL;
326 reg = bank->base;
327
328 switch (bank->method) {
329#ifdef CONFIG_ARCH_OMAP1
330 case METHOD_MPUIO:
331 reg += OMAP_MPUIO_OUTPUT / bank->stride;
332 break;
333#endif
334#ifdef CONFIG_ARCH_OMAP15XX
335 case METHOD_GPIO_1510:
336 reg += OMAP1510_GPIO_DATA_OUTPUT;
337 break;
338#endif
339#ifdef CONFIG_ARCH_OMAP16XX
340 case METHOD_GPIO_1610:
341 reg += OMAP1610_GPIO_DATAOUT;
342 break;
343#endif
344#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
345 case METHOD_GPIO_7XX:
346 reg += OMAP7XX_GPIO_DATA_OUTPUT;
347 break;
348#endif
349#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
350 case METHOD_GPIO_24XX:
351 reg += OMAP24XX_GPIO_DATAOUT;
352 break;
353#endif
354#ifdef CONFIG_ARCH_OMAP4
355 case METHOD_GPIO_44XX:
356 reg += OMAP4_GPIO_DATAOUT;
357 break;
358#endif
359 default:
360 return -EINVAL;
361 }
362
363 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
364}
365
366#define MOD_REG_BIT(reg, bit_mask, set) \
367do { \
368 int l = __raw_readl(base + reg); \
369 if (set) l |= bit_mask; \
370 else l &= ~bit_mask; \
371 __raw_writel(l, base + reg); \
372} while(0)
373
374/**
375 * _set_gpio_debounce - low level gpio debounce time
376 * @bank: the gpio bank we're acting upon
377 * @gpio: the gpio number on this @gpio
378 * @debounce: debounce time to use
379 *
380 * OMAP's debounce time is in 31us steps so we need
381 * to convert and round up to the closest unit.
382 */
383static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
384 unsigned debounce)
385{
386 void __iomem *reg = bank->base;
387 u32 val;
388 u32 l;
389
390 if (!bank->dbck_flag)
391 return;
392
393 if (debounce < 32)
394 debounce = 0x01;
395 else if (debounce > 7936)
396 debounce = 0xff;
397 else
398 debounce = (debounce / 0x1f) - 1;
399
400 l = 1 << get_gpio_index(gpio);
401
402 if (bank->method == METHOD_GPIO_44XX)
403 reg += OMAP4_GPIO_DEBOUNCINGTIME;
404 else
405 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
406
407 __raw_writel(debounce, reg);
408
409 reg = bank->base;
410 if (bank->method == METHOD_GPIO_44XX)
411 reg += OMAP4_GPIO_DEBOUNCENABLE;
412 else
413 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
414
415 val = __raw_readl(reg);
416
417 if (debounce) {
418 val |= l;
419 clk_enable(bank->dbck);
420 } else {
421 val &= ~l;
422 clk_disable(bank->dbck);
423 }
424 bank->dbck_enable_mask = val;
425
426 __raw_writel(val, reg);
427}
428
429#ifdef CONFIG_ARCH_OMAP2PLUS
430static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
431 int trigger)
432{
433 void __iomem *base = bank->base;
434 u32 gpio_bit = 1 << gpio;
435 u32 val;
436
437 if (cpu_is_omap44xx()) {
438 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
439 trigger & IRQ_TYPE_LEVEL_LOW);
440 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
441 trigger & IRQ_TYPE_LEVEL_HIGH);
442 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
443 trigger & IRQ_TYPE_EDGE_RISING);
444 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
445 trigger & IRQ_TYPE_EDGE_FALLING);
446 } else {
447 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
448 trigger & IRQ_TYPE_LEVEL_LOW);
449 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
450 trigger & IRQ_TYPE_LEVEL_HIGH);
451 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
452 trigger & IRQ_TYPE_EDGE_RISING);
453 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
454 trigger & IRQ_TYPE_EDGE_FALLING);
455 }
456 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
457 if (cpu_is_omap44xx()) {
458 if (trigger != 0)
459 __raw_writel(1 << gpio, bank->base+
460 OMAP4_GPIO_IRQWAKEN0);
461 else {
462 val = __raw_readl(bank->base +
463 OMAP4_GPIO_IRQWAKEN0);
464 __raw_writel(val & (~(1 << gpio)), bank->base +
465 OMAP4_GPIO_IRQWAKEN0);
466 }
467 } else {
468 /*
469 * GPIO wakeup request can only be generated on edge
470 * transitions
471 */
472 if (trigger & IRQ_TYPE_EDGE_BOTH)
473 __raw_writel(1 << gpio, bank->base
474 + OMAP24XX_GPIO_SETWKUENA);
475 else
476 __raw_writel(1 << gpio, bank->base
477 + OMAP24XX_GPIO_CLEARWKUENA);
478 }
479 }
480 /* This part needs to be executed always for OMAP34xx */
481 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
482 /*
483 * Log the edge gpio and manually trigger the IRQ
484 * after resume if the input level changes
485 * to avoid irq lost during PER RET/OFF mode
486 * Applies for omap2 non-wakeup gpio and all omap3 gpios
487 */
488 if (trigger & IRQ_TYPE_EDGE_BOTH)
489 bank->enabled_non_wakeup_gpios |= gpio_bit;
490 else
491 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
492 }
493
494 if (cpu_is_omap44xx()) {
495 bank->level_mask =
496 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
497 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
498 } else {
499 bank->level_mask =
500 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
501 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
502 }
503}
504#endif
505
506#ifdef CONFIG_ARCH_OMAP1
507/*
508 * This only applies to chips that can't do both rising and falling edge
509 * detection at once. For all other chips, this function is a noop.
510 */
511static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
512{
513 void __iomem *reg = bank->base;
514 u32 l = 0;
515
516 switch (bank->method) {
517 case METHOD_MPUIO:
518 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
519 break;
520#ifdef CONFIG_ARCH_OMAP15XX
521 case METHOD_GPIO_1510:
522 reg += OMAP1510_GPIO_INT_CONTROL;
523 break;
524#endif
525#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
526 case METHOD_GPIO_7XX:
527 reg += OMAP7XX_GPIO_INT_CONTROL;
528 break;
529#endif
530 default:
531 return;
532 }
533
534 l = __raw_readl(reg);
535 if ((l >> gpio) & 1)
536 l &= ~(1 << gpio);
537 else
538 l |= 1 << gpio;
539
540 __raw_writel(l, reg);
541}
542#endif
543
544static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
545{
546 void __iomem *reg = bank->base;
547 u32 l = 0;
548
549 switch (bank->method) {
550#ifdef CONFIG_ARCH_OMAP1
551 case METHOD_MPUIO:
552 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
553 l = __raw_readl(reg);
554 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
555 bank->toggle_mask |= 1 << gpio;
556 if (trigger & IRQ_TYPE_EDGE_RISING)
557 l |= 1 << gpio;
558 else if (trigger & IRQ_TYPE_EDGE_FALLING)
559 l &= ~(1 << gpio);
560 else
561 goto bad;
562 break;
563#endif
564#ifdef CONFIG_ARCH_OMAP15XX
565 case METHOD_GPIO_1510:
566 reg += OMAP1510_GPIO_INT_CONTROL;
567 l = __raw_readl(reg);
568 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
569 bank->toggle_mask |= 1 << gpio;
570 if (trigger & IRQ_TYPE_EDGE_RISING)
571 l |= 1 << gpio;
572 else if (trigger & IRQ_TYPE_EDGE_FALLING)
573 l &= ~(1 << gpio);
574 else
575 goto bad;
576 break;
577#endif
578#ifdef CONFIG_ARCH_OMAP16XX
579 case METHOD_GPIO_1610:
580 if (gpio & 0x08)
581 reg += OMAP1610_GPIO_EDGE_CTRL2;
582 else
583 reg += OMAP1610_GPIO_EDGE_CTRL1;
584 gpio &= 0x07;
585 l = __raw_readl(reg);
586 l &= ~(3 << (gpio << 1));
587 if (trigger & IRQ_TYPE_EDGE_RISING)
588 l |= 2 << (gpio << 1);
589 if (trigger & IRQ_TYPE_EDGE_FALLING)
590 l |= 1 << (gpio << 1);
591 if (trigger)
592 /* Enable wake-up during idle for dynamic tick */
593 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
594 else
595 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
596 break;
597#endif
598#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
599 case METHOD_GPIO_7XX:
600 reg += OMAP7XX_GPIO_INT_CONTROL;
601 l = __raw_readl(reg);
602 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
603 bank->toggle_mask |= 1 << gpio;
604 if (trigger & IRQ_TYPE_EDGE_RISING)
605 l |= 1 << gpio;
606 else if (trigger & IRQ_TYPE_EDGE_FALLING)
607 l &= ~(1 << gpio);
608 else
609 goto bad;
610 break;
611#endif
612#ifdef CONFIG_ARCH_OMAP2PLUS
613 case METHOD_GPIO_24XX:
614 case METHOD_GPIO_44XX:
615 set_24xx_gpio_triggering(bank, gpio, trigger);
616 return 0;
617#endif
618 default:
619 goto bad;
620 }
621 __raw_writel(l, reg);
622 return 0;
623bad:
624 return -EINVAL;
625}
626
627static int gpio_irq_type(struct irq_data *d, unsigned type)
628{
629 struct gpio_bank *bank;
630 unsigned gpio;
631 int retval;
632 unsigned long flags;
633
634 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
635 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
636 else
637 gpio = d->irq - IH_GPIO_BASE;
638
639 if (check_gpio(gpio) < 0)
640 return -EINVAL;
641
642 if (type & ~IRQ_TYPE_SENSE_MASK)
643 return -EINVAL;
644
645 /* OMAP1 allows only only edge triggering */
646 if (!cpu_class_is_omap2()
647 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
648 return -EINVAL;
649
650 bank = irq_data_get_irq_chip_data(d);
651 spin_lock_irqsave(&bank->lock, flags);
652 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
653 spin_unlock_irqrestore(&bank->lock, flags);
654
655 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
656 __irq_set_handler_locked(d->irq, handle_level_irq);
657 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
658 __irq_set_handler_locked(d->irq, handle_edge_irq);
659
660 return retval;
661}
662
663static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
664{
665 void __iomem *reg = bank->base;
666
667 switch (bank->method) {
668#ifdef CONFIG_ARCH_OMAP1
669 case METHOD_MPUIO:
670 /* MPUIO irqstatus is reset by reading the status register,
671 * so do nothing here */
672 return;
673#endif
674#ifdef CONFIG_ARCH_OMAP15XX
675 case METHOD_GPIO_1510:
676 reg += OMAP1510_GPIO_INT_STATUS;
677 break;
678#endif
679#ifdef CONFIG_ARCH_OMAP16XX
680 case METHOD_GPIO_1610:
681 reg += OMAP1610_GPIO_IRQSTATUS1;
682 break;
683#endif
684#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
685 case METHOD_GPIO_7XX:
686 reg += OMAP7XX_GPIO_INT_STATUS;
687 break;
688#endif
689#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
690 case METHOD_GPIO_24XX:
691 reg += OMAP24XX_GPIO_IRQSTATUS1;
692 break;
693#endif
694#if defined(CONFIG_ARCH_OMAP4)
695 case METHOD_GPIO_44XX:
696 reg += OMAP4_GPIO_IRQSTATUS0;
697 break;
698#endif
699 default:
700 WARN_ON(1);
701 return;
702 }
703 __raw_writel(gpio_mask, reg);
704
705 /* Workaround for clearing DSP GPIO interrupts to allow retention */
706 if (cpu_is_omap24xx() || cpu_is_omap34xx())
707 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
708 else if (cpu_is_omap44xx())
709 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
710
711 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
712 __raw_writel(gpio_mask, reg);
713
714 /* Flush posted write for the irq status to avoid spurious interrupts */
715 __raw_readl(reg);
716 }
717}
718
719static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
720{
721 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
722}
723
724static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
725{
726 void __iomem *reg = bank->base;
727 int inv = 0;
728 u32 l;
729 u32 mask;
730
731 switch (bank->method) {
732#ifdef CONFIG_ARCH_OMAP1
733 case METHOD_MPUIO:
734 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
735 mask = 0xffff;
736 inv = 1;
737 break;
738#endif
739#ifdef CONFIG_ARCH_OMAP15XX
740 case METHOD_GPIO_1510:
741 reg += OMAP1510_GPIO_INT_MASK;
742 mask = 0xffff;
743 inv = 1;
744 break;
745#endif
746#ifdef CONFIG_ARCH_OMAP16XX
747 case METHOD_GPIO_1610:
748 reg += OMAP1610_GPIO_IRQENABLE1;
749 mask = 0xffff;
750 break;
751#endif
752#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
753 case METHOD_GPIO_7XX:
754 reg += OMAP7XX_GPIO_INT_MASK;
755 mask = 0xffffffff;
756 inv = 1;
757 break;
758#endif
759#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
760 case METHOD_GPIO_24XX:
761 reg += OMAP24XX_GPIO_IRQENABLE1;
762 mask = 0xffffffff;
763 break;
764#endif
765#if defined(CONFIG_ARCH_OMAP4)
766 case METHOD_GPIO_44XX:
767 reg += OMAP4_GPIO_IRQSTATUSSET0;
768 mask = 0xffffffff;
769 break;
770#endif
771 default:
772 WARN_ON(1);
773 return 0;
774 }
775
776 l = __raw_readl(reg);
777 if (inv)
778 l = ~l;
779 l &= mask;
780 return l;
781}
782
783static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
784{
785 void __iomem *reg = bank->base;
786 u32 l;
787
788 switch (bank->method) {
789#ifdef CONFIG_ARCH_OMAP1
790 case METHOD_MPUIO:
791 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
792 l = __raw_readl(reg);
793 if (enable)
794 l &= ~(gpio_mask);
795 else
796 l |= gpio_mask;
797 break;
798#endif
799#ifdef CONFIG_ARCH_OMAP15XX
800 case METHOD_GPIO_1510:
801 reg += OMAP1510_GPIO_INT_MASK;
802 l = __raw_readl(reg);
803 if (enable)
804 l &= ~(gpio_mask);
805 else
806 l |= gpio_mask;
807 break;
808#endif
809#ifdef CONFIG_ARCH_OMAP16XX
810 case METHOD_GPIO_1610:
811 if (enable)
812 reg += OMAP1610_GPIO_SET_IRQENABLE1;
813 else
814 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
815 l = gpio_mask;
816 break;
817#endif
818#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
819 case METHOD_GPIO_7XX:
820 reg += OMAP7XX_GPIO_INT_MASK;
821 l = __raw_readl(reg);
822 if (enable)
823 l &= ~(gpio_mask);
824 else
825 l |= gpio_mask;
826 break;
827#endif
828#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
829 case METHOD_GPIO_24XX:
830 if (enable)
831 reg += OMAP24XX_GPIO_SETIRQENABLE1;
832 else
833 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
834 l = gpio_mask;
835 break;
836#endif
837#ifdef CONFIG_ARCH_OMAP4
838 case METHOD_GPIO_44XX:
839 if (enable)
840 reg += OMAP4_GPIO_IRQSTATUSSET0;
841 else
842 reg += OMAP4_GPIO_IRQSTATUSCLR0;
843 l = gpio_mask;
844 break;
845#endif
846 default:
847 WARN_ON(1);
848 return;
849 }
850 __raw_writel(l, reg);
851}
852
853static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
854{
855 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
856}
857
858/*
859 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
860 * 1510 does not seem to have a wake-up register. If JTAG is connected
861 * to the target, system will wake up always on GPIO events. While
862 * system is running all registered GPIO interrupts need to have wake-up
863 * enabled. When system is suspended, only selected GPIO interrupts need
864 * to have wake-up enabled.
865 */
866static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
867{
868 unsigned long uninitialized_var(flags);
869
870 switch (bank->method) {
871#ifdef CONFIG_ARCH_OMAP16XX
872 case METHOD_MPUIO:
873 case METHOD_GPIO_1610:
874 spin_lock_irqsave(&bank->lock, flags);
875 if (enable)
876 bank->suspend_wakeup |= (1 << gpio);
877 else
878 bank->suspend_wakeup &= ~(1 << gpio);
879 spin_unlock_irqrestore(&bank->lock, flags);
880 return 0;
881#endif
882#ifdef CONFIG_ARCH_OMAP2PLUS
883 case METHOD_GPIO_24XX:
884 case METHOD_GPIO_44XX:
885 if (bank->non_wakeup_gpios & (1 << gpio)) {
886 printk(KERN_ERR "Unable to modify wakeup on "
887 "non-wakeup GPIO%d\n",
888 (bank - gpio_bank) * 32 + gpio);
889 return -EINVAL;
890 }
891 spin_lock_irqsave(&bank->lock, flags);
892 if (enable)
893 bank->suspend_wakeup |= (1 << gpio);
894 else
895 bank->suspend_wakeup &= ~(1 << gpio);
896 spin_unlock_irqrestore(&bank->lock, flags);
897 return 0;
898#endif
899 default:
900 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
901 bank->method);
902 return -EINVAL;
903 }
904}
905
906static void _reset_gpio(struct gpio_bank *bank, int gpio)
907{
908 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
909 _set_gpio_irqenable(bank, gpio, 0);
910 _clear_gpio_irqstatus(bank, gpio);
911 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
912}
913
914/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
915static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
916{
917 unsigned int gpio = d->irq - IH_GPIO_BASE;
918 struct gpio_bank *bank;
919 int retval;
920
921 if (check_gpio(gpio) < 0)
922 return -ENODEV;
923 bank = irq_data_get_irq_chip_data(d);
924 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
925
926 return retval;
927}
928
929static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
930{
931 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
932 unsigned long flags;
933
934 spin_lock_irqsave(&bank->lock, flags);
935
936 /* Set trigger to none. You need to enable the desired trigger with
937 * request_irq() or set_irq_type().
938 */
939 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
940
941#ifdef CONFIG_ARCH_OMAP15XX
942 if (bank->method == METHOD_GPIO_1510) {
943 void __iomem *reg;
944
945 /* Claim the pin for MPU */
946 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
947 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
948 }
949#endif
950 if (!cpu_class_is_omap1()) {
951 if (!bank->mod_usage) {
952 void __iomem *reg = bank->base;
953 u32 ctrl;
954
955 if (cpu_is_omap24xx() || cpu_is_omap34xx())
956 reg += OMAP24XX_GPIO_CTRL;
957 else if (cpu_is_omap44xx())
958 reg += OMAP4_GPIO_CTRL;
959 ctrl = __raw_readl(reg);
960 /* Module is enabled, clocks are not gated */
961 ctrl &= 0xFFFFFFFE;
962 __raw_writel(ctrl, reg);
963 }
964 bank->mod_usage |= 1 << offset;
965 }
966 spin_unlock_irqrestore(&bank->lock, flags);
967
968 return 0;
969}
970
971static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
972{
973 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
974 unsigned long flags;
975
976 spin_lock_irqsave(&bank->lock, flags);
977#ifdef CONFIG_ARCH_OMAP16XX
978 if (bank->method == METHOD_GPIO_1610) {
979 /* Disable wake-up during idle for dynamic tick */
980 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
981 __raw_writel(1 << offset, reg);
982 }
983#endif
984#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
985 if (bank->method == METHOD_GPIO_24XX) {
986 /* Disable wake-up during idle for dynamic tick */
987 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
988 __raw_writel(1 << offset, reg);
989 }
990#endif
991#ifdef CONFIG_ARCH_OMAP4
992 if (bank->method == METHOD_GPIO_44XX) {
993 /* Disable wake-up during idle for dynamic tick */
994 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
995 __raw_writel(1 << offset, reg);
996 }
997#endif
998 if (!cpu_class_is_omap1()) {
999 bank->mod_usage &= ~(1 << offset);
1000 if (!bank->mod_usage) {
1001 void __iomem *reg = bank->base;
1002 u32 ctrl;
1003
1004 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1005 reg += OMAP24XX_GPIO_CTRL;
1006 else if (cpu_is_omap44xx())
1007 reg += OMAP4_GPIO_CTRL;
1008 ctrl = __raw_readl(reg);
1009 /* Module is disabled, clocks are gated */
1010 ctrl |= 1;
1011 __raw_writel(ctrl, reg);
1012 }
1013 }
1014 _reset_gpio(bank, bank->chip.base + offset);
1015 spin_unlock_irqrestore(&bank->lock, flags);
1016}
1017
1018/*
1019 * We need to unmask the GPIO bank interrupt as soon as possible to
1020 * avoid missing GPIO interrupts for other lines in the bank.
1021 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1022 * in the bank to avoid missing nested interrupts for a GPIO line.
1023 * If we wait to unmask individual GPIO lines in the bank after the
1024 * line's interrupt handler has been run, we may miss some nested
1025 * interrupts.
1026 */
1027static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1028{
1029 void __iomem *isr_reg = NULL;
1030 u32 isr;
1031 unsigned int gpio_irq, gpio_index;
1032 struct gpio_bank *bank;
1033 u32 retrigger = 0;
1034 int unmasked = 0;
1035 struct irq_chip *chip = irq_desc_get_chip(desc);
1036
1037 chained_irq_enter(chip, desc);
1038
1039 bank = irq_get_handler_data(irq);
1040#ifdef CONFIG_ARCH_OMAP1
1041 if (bank->method == METHOD_MPUIO)
1042 isr_reg = bank->base +
1043 OMAP_MPUIO_GPIO_INT / bank->stride;
1044#endif
1045#ifdef CONFIG_ARCH_OMAP15XX
1046 if (bank->method == METHOD_GPIO_1510)
1047 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1048#endif
1049#if defined(CONFIG_ARCH_OMAP16XX)
1050 if (bank->method == METHOD_GPIO_1610)
1051 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1052#endif
1053#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1054 if (bank->method == METHOD_GPIO_7XX)
1055 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1056#endif
1057#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1058 if (bank->method == METHOD_GPIO_24XX)
1059 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1060#endif
1061#if defined(CONFIG_ARCH_OMAP4)
1062 if (bank->method == METHOD_GPIO_44XX)
1063 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1064#endif
1065
1066 if (WARN_ON(!isr_reg))
1067 goto exit;
1068
1069 while(1) {
1070 u32 isr_saved, level_mask = 0;
1071 u32 enabled;
1072
1073 enabled = _get_gpio_irqbank_mask(bank);
1074 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1075
1076 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1077 isr &= 0x0000ffff;
1078
1079 if (cpu_class_is_omap2()) {
1080 level_mask = bank->level_mask & enabled;
1081 }
1082
1083 /* clear edge sensitive interrupts before handler(s) are
1084 called so that we don't miss any interrupt occurred while
1085 executing them */
1086 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1087 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1088 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1089
1090 /* if there is only edge sensitive GPIO pin interrupts
1091 configured, we could unmask GPIO bank interrupt immediately */
1092 if (!level_mask && !unmasked) {
1093 unmasked = 1;
1094 chained_irq_exit(chip, desc);
1095 }
1096
1097 isr |= retrigger;
1098 retrigger = 0;
1099 if (!isr)
1100 break;
1101
1102 gpio_irq = bank->virtual_irq_start;
1103 for (; isr != 0; isr >>= 1, gpio_irq++) {
1104 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1105
1106 if (!(isr & 1))
1107 continue;
1108
1109#ifdef CONFIG_ARCH_OMAP1
1110 /*
1111 * Some chips can't respond to both rising and falling
1112 * at the same time. If this irq was requested with
1113 * both flags, we need to flip the ICR data for the IRQ
1114 * to respond to the IRQ for the opposite direction.
1115 * This will be indicated in the bank toggle_mask.
1116 */
1117 if (bank->toggle_mask & (1 << gpio_index))
1118 _toggle_gpio_edge_triggering(bank, gpio_index);
1119#endif
1120
1121 generic_handle_irq(gpio_irq);
1122 }
1123 }
1124 /* if bank has any level sensitive GPIO pin interrupt
1125 configured, we must unmask the bank interrupt only after
1126 handler(s) are executed in order to avoid spurious bank
1127 interrupt */
1128exit:
1129 if (!unmasked)
1130 chained_irq_exit(chip, desc);
1131}
1132
1133static void gpio_irq_shutdown(struct irq_data *d)
1134{
1135 unsigned int gpio = d->irq - IH_GPIO_BASE;
1136 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1137
1138 _reset_gpio(bank, gpio);
1139}
1140
1141static void gpio_ack_irq(struct irq_data *d)
1142{
1143 unsigned int gpio = d->irq - IH_GPIO_BASE;
1144 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1145
1146 _clear_gpio_irqstatus(bank, gpio);
1147}
1148
1149static void gpio_mask_irq(struct irq_data *d)
1150{
1151 unsigned int gpio = d->irq - IH_GPIO_BASE;
1152 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1153
1154 _set_gpio_irqenable(bank, gpio, 0);
1155 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1156}
1157
1158static void gpio_unmask_irq(struct irq_data *d)
1159{
1160 unsigned int gpio = d->irq - IH_GPIO_BASE;
1161 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1162 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1163 u32 trigger = irqd_get_trigger_type(d);
1164
1165 if (trigger)
1166 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1167
1168 /* For level-triggered GPIOs, the clearing must be done after
1169 * the HW source is cleared, thus after the handler has run */
1170 if (bank->level_mask & irq_mask) {
1171 _set_gpio_irqenable(bank, gpio, 0);
1172 _clear_gpio_irqstatus(bank, gpio);
1173 }
1174
1175 _set_gpio_irqenable(bank, gpio, 1);
1176}
1177
1178static struct irq_chip gpio_irq_chip = {
1179 .name = "GPIO",
1180 .irq_shutdown = gpio_irq_shutdown,
1181 .irq_ack = gpio_ack_irq,
1182 .irq_mask = gpio_mask_irq,
1183 .irq_unmask = gpio_unmask_irq,
1184 .irq_set_type = gpio_irq_type,
1185 .irq_set_wake = gpio_wake_enable,
1186};
1187
1188/*---------------------------------------------------------------------*/
1189
1190#ifdef CONFIG_ARCH_OMAP1
1191
1192/* MPUIO uses the always-on 32k clock */
1193
1194static void mpuio_ack_irq(struct irq_data *d)
1195{
1196 /* The ISR is reset automatically, so do nothing here. */
1197}
1198
1199static void mpuio_mask_irq(struct irq_data *d)
1200{
1201 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1202 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1203
1204 _set_gpio_irqenable(bank, gpio, 0);
1205}
1206
1207static void mpuio_unmask_irq(struct irq_data *d)
1208{
1209 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1210 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1211
1212 _set_gpio_irqenable(bank, gpio, 1);
1213}
1214
1215static struct irq_chip mpuio_irq_chip = {
1216 .name = "MPUIO",
1217 .irq_ack = mpuio_ack_irq,
1218 .irq_mask = mpuio_mask_irq,
1219 .irq_unmask = mpuio_unmask_irq,
1220 .irq_set_type = gpio_irq_type,
1221#ifdef CONFIG_ARCH_OMAP16XX
1222 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1223 .irq_set_wake = gpio_wake_enable,
1224#endif
1225};
1226
1227
1228#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1229
1230
1231#ifdef CONFIG_ARCH_OMAP16XX
1232
1233#include <linux/platform_device.h>
1234
1235static int omap_mpuio_suspend_noirq(struct device *dev)
1236{
1237 struct platform_device *pdev = to_platform_device(dev);
1238 struct gpio_bank *bank = platform_get_drvdata(pdev);
1239 void __iomem *mask_reg = bank->base +
1240 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1241 unsigned long flags;
1242
1243 spin_lock_irqsave(&bank->lock, flags);
1244 bank->saved_wakeup = __raw_readl(mask_reg);
1245 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1246 spin_unlock_irqrestore(&bank->lock, flags);
1247
1248 return 0;
1249}
1250
1251static int omap_mpuio_resume_noirq(struct device *dev)
1252{
1253 struct platform_device *pdev = to_platform_device(dev);
1254 struct gpio_bank *bank = platform_get_drvdata(pdev);
1255 void __iomem *mask_reg = bank->base +
1256 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1257 unsigned long flags;
1258
1259 spin_lock_irqsave(&bank->lock, flags);
1260 __raw_writel(bank->saved_wakeup, mask_reg);
1261 spin_unlock_irqrestore(&bank->lock, flags);
1262
1263 return 0;
1264}
1265
1266static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1267 .suspend_noirq = omap_mpuio_suspend_noirq,
1268 .resume_noirq = omap_mpuio_resume_noirq,
1269};
1270
1271/* use platform_driver for this. */
1272static struct platform_driver omap_mpuio_driver = {
1273 .driver = {
1274 .name = "mpuio",
1275 .pm = &omap_mpuio_dev_pm_ops,
1276 },
1277};
1278
1279static struct platform_device omap_mpuio_device = {
1280 .name = "mpuio",
1281 .id = -1,
1282 .dev = {
1283 .driver = &omap_mpuio_driver.driver,
1284 }
1285 /* could list the /proc/iomem resources */
1286};
1287
1288static inline void mpuio_init(void)
1289{
1290 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1291 platform_set_drvdata(&omap_mpuio_device, bank);
1292
1293 if (platform_driver_register(&omap_mpuio_driver) == 0)
1294 (void) platform_device_register(&omap_mpuio_device);
1295}
1296
1297#else
1298static inline void mpuio_init(void) {}
1299#endif /* 16xx */
1300
1301#else
1302
1303extern struct irq_chip mpuio_irq_chip;
1304
1305#define bank_is_mpuio(bank) 0
1306static inline void mpuio_init(void) {}
1307
1308#endif
1309
1310/*---------------------------------------------------------------------*/
1311
1312/* REVISIT these are stupid implementations! replace by ones that
1313 * don't switch on METHOD_* and which mostly avoid spinlocks
1314 */
1315
1316static int gpio_input(struct gpio_chip *chip, unsigned offset)
1317{
1318 struct gpio_bank *bank;
1319 unsigned long flags;
1320
1321 bank = container_of(chip, struct gpio_bank, chip);
1322 spin_lock_irqsave(&bank->lock, flags);
1323 _set_gpio_direction(bank, offset, 1);
1324 spin_unlock_irqrestore(&bank->lock, flags);
1325 return 0;
1326}
1327
1328static int gpio_is_input(struct gpio_bank *bank, int mask)
1329{
1330 void __iomem *reg = bank->base;
1331
1332 switch (bank->method) {
1333 case METHOD_MPUIO:
1334 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1335 break;
1336 case METHOD_GPIO_1510:
1337 reg += OMAP1510_GPIO_DIR_CONTROL;
1338 break;
1339 case METHOD_GPIO_1610:
1340 reg += OMAP1610_GPIO_DIRECTION;
1341 break;
1342 case METHOD_GPIO_7XX:
1343 reg += OMAP7XX_GPIO_DIR_CONTROL;
1344 break;
1345 case METHOD_GPIO_24XX:
1346 reg += OMAP24XX_GPIO_OE;
1347 break;
1348 case METHOD_GPIO_44XX:
1349 reg += OMAP4_GPIO_OE;
1350 break;
1351 default:
1352 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1353 return -EINVAL;
1354 }
1355 return __raw_readl(reg) & mask;
1356}
1357
1358static int gpio_get(struct gpio_chip *chip, unsigned offset)
1359{
1360 struct gpio_bank *bank;
1361 void __iomem *reg;
1362 int gpio;
1363 u32 mask;
1364
1365 gpio = chip->base + offset;
1366 bank = get_gpio_bank(gpio);
1367 reg = bank->base;
1368 mask = 1 << get_gpio_index(gpio);
1369
1370 if (gpio_is_input(bank, mask))
1371 return _get_gpio_datain(bank, gpio);
1372 else
1373 return _get_gpio_dataout(bank, gpio);
1374}
1375
1376static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1377{
1378 struct gpio_bank *bank;
1379 unsigned long flags;
1380
1381 bank = container_of(chip, struct gpio_bank, chip);
1382 spin_lock_irqsave(&bank->lock, flags);
1383 _set_gpio_dataout(bank, offset, value);
1384 _set_gpio_direction(bank, offset, 0);
1385 spin_unlock_irqrestore(&bank->lock, flags);
1386 return 0;
1387}
1388
1389static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1390 unsigned debounce)
1391{
1392 struct gpio_bank *bank;
1393 unsigned long flags;
1394
1395 bank = container_of(chip, struct gpio_bank, chip);
1396
1397 if (!bank->dbck) {
1398 bank->dbck = clk_get(bank->dev, "dbclk");
1399 if (IS_ERR(bank->dbck))
1400 dev_err(bank->dev, "Could not get gpio dbck\n");
1401 }
1402
1403 spin_lock_irqsave(&bank->lock, flags);
1404 _set_gpio_debounce(bank, offset, debounce);
1405 spin_unlock_irqrestore(&bank->lock, flags);
1406
1407 return 0;
1408}
1409
1410static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1411{
1412 struct gpio_bank *bank;
1413 unsigned long flags;
1414
1415 bank = container_of(chip, struct gpio_bank, chip);
1416 spin_lock_irqsave(&bank->lock, flags);
1417 _set_gpio_dataout(bank, offset, value);
1418 spin_unlock_irqrestore(&bank->lock, flags);
1419}
1420
1421static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1422{
1423 struct gpio_bank *bank;
1424
1425 bank = container_of(chip, struct gpio_bank, chip);
1426 return bank->virtual_irq_start + offset;
1427}
1428
1429/*---------------------------------------------------------------------*/
1430
1431static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1432{
1433 u32 rev;
1434
1435 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1436 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1437 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1438 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1439 else if (cpu_is_omap44xx())
1440 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1441 else
1442 return;
1443
1444 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1445 (rev >> 4) & 0x0f, rev & 0x0f);
1446}
1447
1448/* This lock class tells lockdep that GPIO irqs are in a different
1449 * category than their parents, so it won't report false recursion.
1450 */
1451static struct lock_class_key gpio_lock_class;
1452
1453static inline int init_gpio_info(struct platform_device *pdev)
1454{
1455 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1456 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1457 GFP_KERNEL);
1458 if (!gpio_bank) {
1459 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1460 return -ENOMEM;
1461 }
1462 return 0;
1463}
1464
1465/* TODO: Cleanup cpu_is_* checks */
1466static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1467{
1468 if (cpu_class_is_omap2()) {
1469 if (cpu_is_omap44xx()) {
1470 __raw_writel(0xffffffff, bank->base +
1471 OMAP4_GPIO_IRQSTATUSCLR0);
1472 __raw_writel(0x00000000, bank->base +
1473 OMAP4_GPIO_DEBOUNCENABLE);
1474 /* Initialize interface clk ungated, module enabled */
1475 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1476 } else if (cpu_is_omap34xx()) {
1477 __raw_writel(0x00000000, bank->base +
1478 OMAP24XX_GPIO_IRQENABLE1);
1479 __raw_writel(0xffffffff, bank->base +
1480 OMAP24XX_GPIO_IRQSTATUS1);
1481 __raw_writel(0x00000000, bank->base +
1482 OMAP24XX_GPIO_DEBOUNCE_EN);
1483
1484 /* Initialize interface clk ungated, module enabled */
1485 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1486 } else if (cpu_is_omap24xx()) {
1487 static const u32 non_wakeup_gpios[] = {
1488 0xe203ffc0, 0x08700040
1489 };
1490 if (id < ARRAY_SIZE(non_wakeup_gpios))
1491 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1492 }
1493 } else if (cpu_class_is_omap1()) {
1494 if (bank_is_mpuio(bank))
1495 __raw_writew(0xffff, bank->base +
1496 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1497 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1498 __raw_writew(0xffff, bank->base
1499 + OMAP1510_GPIO_INT_MASK);
1500 __raw_writew(0x0000, bank->base
1501 + OMAP1510_GPIO_INT_STATUS);
1502 }
1503 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1504 __raw_writew(0x0000, bank->base
1505 + OMAP1610_GPIO_IRQENABLE1);
1506 __raw_writew(0xffff, bank->base
1507 + OMAP1610_GPIO_IRQSTATUS1);
1508 __raw_writew(0x0014, bank->base
1509 + OMAP1610_GPIO_SYSCONFIG);
1510
1511 /*
1512 * Enable system clock for GPIO module.
1513 * The CAM_CLK_CTRL *is* really the right place.
1514 */
1515 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1516 ULPD_CAM_CLK_CTRL);
1517 }
1518 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1519 __raw_writel(0xffffffff, bank->base
1520 + OMAP7XX_GPIO_INT_MASK);
1521 __raw_writel(0x00000000, bank->base
1522 + OMAP7XX_GPIO_INT_STATUS);
1523 }
1524 }
1525}
1526
1527static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1528{
1529 int j;
1530 static int gpio;
1531
1532 bank->mod_usage = 0;
1533 /*
1534 * REVISIT eventually switch from OMAP-specific gpio structs
1535 * over to the generic ones
1536 */
1537 bank->chip.request = omap_gpio_request;
1538 bank->chip.free = omap_gpio_free;
1539 bank->chip.direction_input = gpio_input;
1540 bank->chip.get = gpio_get;
1541 bank->chip.direction_output = gpio_output;
1542 bank->chip.set_debounce = gpio_debounce;
1543 bank->chip.set = gpio_set;
1544 bank->chip.to_irq = gpio_2irq;
1545 if (bank_is_mpuio(bank)) {
1546 bank->chip.label = "mpuio";
1547#ifdef CONFIG_ARCH_OMAP16XX
1548 bank->chip.dev = &omap_mpuio_device.dev;
1549#endif
1550 bank->chip.base = OMAP_MPUIO(0);
1551 } else {
1552 bank->chip.label = "gpio";
1553 bank->chip.base = gpio;
1554 gpio += bank_width;
1555 }
1556 bank->chip.ngpio = bank_width;
1557
1558 gpiochip_add(&bank->chip);
1559
1560 for (j = bank->virtual_irq_start;
1561 j < bank->virtual_irq_start + bank_width; j++) {
1562 irq_set_lockdep_class(j, &gpio_lock_class);
1563 irq_set_chip_data(j, bank);
1564 if (bank_is_mpuio(bank))
1565 irq_set_chip(j, &mpuio_irq_chip);
1566 else
1567 irq_set_chip(j, &gpio_irq_chip);
1568 irq_set_handler(j, handle_simple_irq);
1569 set_irq_flags(j, IRQF_VALID);
1570 }
1571 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1572 irq_set_handler_data(bank->irq, bank);
1573}
1574
1575static int __devinit omap_gpio_probe(struct platform_device *pdev)
1576{
1577 static int gpio_init_done;
1578 struct omap_gpio_platform_data *pdata;
1579 struct resource *res;
1580 int id;
1581 struct gpio_bank *bank;
1582
1583 if (!pdev->dev.platform_data)
1584 return -EINVAL;
1585
1586 pdata = pdev->dev.platform_data;
1587
1588 if (!gpio_init_done) {
1589 int ret;
1590
1591 ret = init_gpio_info(pdev);
1592 if (ret)
1593 return ret;
1594 }
1595
1596 id = pdev->id;
1597 bank = &gpio_bank[id];
1598
1599 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1600 if (unlikely(!res)) {
1601 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1602 return -ENODEV;
1603 }
1604
1605 bank->irq = res->start;
1606 bank->virtual_irq_start = pdata->virtual_irq_start;
1607 bank->method = pdata->bank_type;
1608 bank->dev = &pdev->dev;
1609 bank->dbck_flag = pdata->dbck_flag;
1610 bank->stride = pdata->bank_stride;
1611 bank_width = pdata->bank_width;
1612
1613 spin_lock_init(&bank->lock);
1614
1615 /* Static mapping, never released */
1616 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1617 if (unlikely(!res)) {
1618 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1619 return -ENODEV;
1620 }
1621
1622 bank->base = ioremap(res->start, resource_size(res));
1623 if (!bank->base) {
1624 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1625 return -ENOMEM;
1626 }
1627
1628 pm_runtime_enable(bank->dev);
1629 pm_runtime_get_sync(bank->dev);
1630
1631 omap_gpio_mod_init(bank, id);
1632 omap_gpio_chip_init(bank);
1633 omap_gpio_show_rev(bank);
1634
1635 if (!gpio_init_done)
1636 gpio_init_done = 1;
1637
1638 return 0;
1639}
1640
1641#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1642static int omap_gpio_suspend(void)
1643{
1644 int i;
1645
1646 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1647 return 0;
1648
1649 for (i = 0; i < gpio_bank_count; i++) {
1650 struct gpio_bank *bank = &gpio_bank[i];
1651 void __iomem *wake_status;
1652 void __iomem *wake_clear;
1653 void __iomem *wake_set;
1654 unsigned long flags;
1655
1656 switch (bank->method) {
1657#ifdef CONFIG_ARCH_OMAP16XX
1658 case METHOD_GPIO_1610:
1659 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1660 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1661 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1662 break;
1663#endif
1664#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1665 case METHOD_GPIO_24XX:
1666 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1667 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1668 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1669 break;
1670#endif
1671#ifdef CONFIG_ARCH_OMAP4
1672 case METHOD_GPIO_44XX:
1673 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1674 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1675 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1676 break;
1677#endif
1678 default:
1679 continue;
1680 }
1681
1682 spin_lock_irqsave(&bank->lock, flags);
1683 bank->saved_wakeup = __raw_readl(wake_status);
1684 __raw_writel(0xffffffff, wake_clear);
1685 __raw_writel(bank->suspend_wakeup, wake_set);
1686 spin_unlock_irqrestore(&bank->lock, flags);
1687 }
1688
1689 return 0;
1690}
1691
1692static void omap_gpio_resume(void)
1693{
1694 int i;
1695
1696 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1697 return;
1698
1699 for (i = 0; i < gpio_bank_count; i++) {
1700 struct gpio_bank *bank = &gpio_bank[i];
1701 void __iomem *wake_clear;
1702 void __iomem *wake_set;
1703 unsigned long flags;
1704
1705 switch (bank->method) {
1706#ifdef CONFIG_ARCH_OMAP16XX
1707 case METHOD_GPIO_1610:
1708 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1709 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1710 break;
1711#endif
1712#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1713 case METHOD_GPIO_24XX:
1714 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1715 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1716 break;
1717#endif
1718#ifdef CONFIG_ARCH_OMAP4
1719 case METHOD_GPIO_44XX:
1720 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1721 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1722 break;
1723#endif
1724 default:
1725 continue;
1726 }
1727
1728 spin_lock_irqsave(&bank->lock, flags);
1729 __raw_writel(0xffffffff, wake_clear);
1730 __raw_writel(bank->saved_wakeup, wake_set);
1731 spin_unlock_irqrestore(&bank->lock, flags);
1732 }
1733}
1734
1735static struct syscore_ops omap_gpio_syscore_ops = {
1736 .suspend = omap_gpio_suspend,
1737 .resume = omap_gpio_resume,
1738};
1739
1740#endif
1741
1742#ifdef CONFIG_ARCH_OMAP2PLUS
1743
1744static int workaround_enabled;
1745
1746void omap2_gpio_prepare_for_idle(int off_mode)
1747{
1748 int i, c = 0;
1749 int min = 0;
1750
1751 if (cpu_is_omap34xx())
1752 min = 1;
1753
1754 for (i = min; i < gpio_bank_count; i++) {
1755 struct gpio_bank *bank = &gpio_bank[i];
1756 u32 l1 = 0, l2 = 0;
1757 int j;
1758
1759 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1760 clk_disable(bank->dbck);
1761
1762 if (!off_mode)
1763 continue;
1764
1765 /* If going to OFF, remove triggering for all
1766 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1767 * generated. See OMAP2420 Errata item 1.101. */
1768 if (!(bank->enabled_non_wakeup_gpios))
1769 continue;
1770
1771 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1772 bank->saved_datain = __raw_readl(bank->base +
1773 OMAP24XX_GPIO_DATAIN);
1774 l1 = __raw_readl(bank->base +
1775 OMAP24XX_GPIO_FALLINGDETECT);
1776 l2 = __raw_readl(bank->base +
1777 OMAP24XX_GPIO_RISINGDETECT);
1778 }
1779
1780 if (cpu_is_omap44xx()) {
1781 bank->saved_datain = __raw_readl(bank->base +
1782 OMAP4_GPIO_DATAIN);
1783 l1 = __raw_readl(bank->base +
1784 OMAP4_GPIO_FALLINGDETECT);
1785 l2 = __raw_readl(bank->base +
1786 OMAP4_GPIO_RISINGDETECT);
1787 }
1788
1789 bank->saved_fallingdetect = l1;
1790 bank->saved_risingdetect = l2;
1791 l1 &= ~bank->enabled_non_wakeup_gpios;
1792 l2 &= ~bank->enabled_non_wakeup_gpios;
1793
1794 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1795 __raw_writel(l1, bank->base +
1796 OMAP24XX_GPIO_FALLINGDETECT);
1797 __raw_writel(l2, bank->base +
1798 OMAP24XX_GPIO_RISINGDETECT);
1799 }
1800
1801 if (cpu_is_omap44xx()) {
1802 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1803 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1804 }
1805
1806 c++;
1807 }
1808 if (!c) {
1809 workaround_enabled = 0;
1810 return;
1811 }
1812 workaround_enabled = 1;
1813}
1814
1815void omap2_gpio_resume_after_idle(void)
1816{
1817 int i;
1818 int min = 0;
1819
1820 if (cpu_is_omap34xx())
1821 min = 1;
1822 for (i = min; i < gpio_bank_count; i++) {
1823 struct gpio_bank *bank = &gpio_bank[i];
1824 u32 l = 0, gen, gen0, gen1;
1825 int j;
1826
1827 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1828 clk_enable(bank->dbck);
1829
1830 if (!workaround_enabled)
1831 continue;
1832
1833 if (!(bank->enabled_non_wakeup_gpios))
1834 continue;
1835
1836 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1837 __raw_writel(bank->saved_fallingdetect,
1838 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1839 __raw_writel(bank->saved_risingdetect,
1840 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1841 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1842 }
1843
1844 if (cpu_is_omap44xx()) {
1845 __raw_writel(bank->saved_fallingdetect,
1846 bank->base + OMAP4_GPIO_FALLINGDETECT);
1847 __raw_writel(bank->saved_risingdetect,
1848 bank->base + OMAP4_GPIO_RISINGDETECT);
1849 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1850 }
1851
1852 /* Check if any of the non-wakeup interrupt GPIOs have changed
1853 * state. If so, generate an IRQ by software. This is
1854 * horribly racy, but it's the best we can do to work around
1855 * this silicon bug. */
1856 l ^= bank->saved_datain;
1857 l &= bank->enabled_non_wakeup_gpios;
1858
1859 /*
1860 * No need to generate IRQs for the rising edge for gpio IRQs
1861 * configured with falling edge only; and vice versa.
1862 */
1863 gen0 = l & bank->saved_fallingdetect;
1864 gen0 &= bank->saved_datain;
1865
1866 gen1 = l & bank->saved_risingdetect;
1867 gen1 &= ~(bank->saved_datain);
1868
1869 /* FIXME: Consider GPIO IRQs with level detections properly! */
1870 gen = l & (~(bank->saved_fallingdetect) &
1871 ~(bank->saved_risingdetect));
1872 /* Consider all GPIO IRQs needed to be updated */
1873 gen |= gen0 | gen1;
1874
1875 if (gen) {
1876 u32 old0, old1;
1877
1878 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1879 old0 = __raw_readl(bank->base +
1880 OMAP24XX_GPIO_LEVELDETECT0);
1881 old1 = __raw_readl(bank->base +
1882 OMAP24XX_GPIO_LEVELDETECT1);
1883 __raw_writel(old0 | gen, bank->base +
1884 OMAP24XX_GPIO_LEVELDETECT0);
1885 __raw_writel(old1 | gen, bank->base +
1886 OMAP24XX_GPIO_LEVELDETECT1);
1887 __raw_writel(old0, bank->base +
1888 OMAP24XX_GPIO_LEVELDETECT0);
1889 __raw_writel(old1, bank->base +
1890 OMAP24XX_GPIO_LEVELDETECT1);
1891 }
1892
1893 if (cpu_is_omap44xx()) {
1894 old0 = __raw_readl(bank->base +
1895 OMAP4_GPIO_LEVELDETECT0);
1896 old1 = __raw_readl(bank->base +
1897 OMAP4_GPIO_LEVELDETECT1);
1898 __raw_writel(old0 | l, bank->base +
1899 OMAP4_GPIO_LEVELDETECT0);
1900 __raw_writel(old1 | l, bank->base +
1901 OMAP4_GPIO_LEVELDETECT1);
1902 __raw_writel(old0, bank->base +
1903 OMAP4_GPIO_LEVELDETECT0);
1904 __raw_writel(old1, bank->base +
1905 OMAP4_GPIO_LEVELDETECT1);
1906 }
1907 }
1908 }
1909
1910}
1911
1912#endif
1913
1914#ifdef CONFIG_ARCH_OMAP3
1915/* save the registers of bank 2-6 */
1916void omap_gpio_save_context(void)
1917{
1918 int i;
1919
1920 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1921 for (i = 1; i < gpio_bank_count; i++) {
1922 struct gpio_bank *bank = &gpio_bank[i];
1923 gpio_context[i].irqenable1 =
1924 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1925 gpio_context[i].irqenable2 =
1926 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1927 gpio_context[i].wake_en =
1928 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1929 gpio_context[i].ctrl =
1930 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1931 gpio_context[i].oe =
1932 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1933 gpio_context[i].leveldetect0 =
1934 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1935 gpio_context[i].leveldetect1 =
1936 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1937 gpio_context[i].risingdetect =
1938 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1939 gpio_context[i].fallingdetect =
1940 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1941 gpio_context[i].dataout =
1942 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
1943 }
1944}
1945
1946/* restore the required registers of bank 2-6 */
1947void omap_gpio_restore_context(void)
1948{
1949 int i;
1950
1951 for (i = 1; i < gpio_bank_count; i++) {
1952 struct gpio_bank *bank = &gpio_bank[i];
1953 __raw_writel(gpio_context[i].irqenable1,
1954 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1955 __raw_writel(gpio_context[i].irqenable2,
1956 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1957 __raw_writel(gpio_context[i].wake_en,
1958 bank->base + OMAP24XX_GPIO_WAKE_EN);
1959 __raw_writel(gpio_context[i].ctrl,
1960 bank->base + OMAP24XX_GPIO_CTRL);
1961 __raw_writel(gpio_context[i].oe,
1962 bank->base + OMAP24XX_GPIO_OE);
1963 __raw_writel(gpio_context[i].leveldetect0,
1964 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1965 __raw_writel(gpio_context[i].leveldetect1,
1966 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1967 __raw_writel(gpio_context[i].risingdetect,
1968 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1969 __raw_writel(gpio_context[i].fallingdetect,
1970 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1971 __raw_writel(gpio_context[i].dataout,
1972 bank->base + OMAP24XX_GPIO_DATAOUT);
1973 }
1974}
1975#endif
1976
1977static struct platform_driver omap_gpio_driver = {
1978 .probe = omap_gpio_probe,
1979 .driver = {
1980 .name = "omap_gpio",
1981 },
1982};
1983
1984/*
1985 * gpio driver register needs to be done before
1986 * machine_init functions access gpio APIs.
1987 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1988 */
1989static int __init omap_gpio_drv_reg(void)
1990{
1991 return platform_driver_register(&omap_gpio_driver);
1992}
1993postcore_initcall(omap_gpio_drv_reg);
1994
1995static int __init omap_gpio_sysinit(void)
1996{
1997 mpuio_init();
1998
1999#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2000 if (cpu_is_omap16xx() || cpu_class_is_omap2())
2001 register_syscore_ops(&omap_gpio_syscore_ops);
2002#endif
2003
2004 return 0;
2005}
2006
2007arch_initcall(omap_gpio_sysinit);
diff --git a/drivers/gpio/gpio-plat-samsung.c b/drivers/gpio/gpio-plat-samsung.c
new file mode 100644
index 000000000000..ea37c0461788
--- /dev/null
+++ b/drivers/gpio/gpio-plat-samsung.c
@@ -0,0 +1,206 @@
1/* arch/arm/plat-samsung/gpiolib.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com/
10 *
11 * SAMSUNG - GPIOlib support
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/kernel.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <plat/gpio-core.h>
23#include <plat/gpio-cfg.h>
24#include <plat/gpio-cfg-helpers.h>
25
26#ifndef DEBUG_GPIO
27#define gpio_dbg(x...) do { } while (0)
28#else
29#define gpio_dbg(x...) printk(KERN_DEBUG x)
30#endif
31
32/* The samsung_gpiolib_4bit routines are to control the gpio banks where
33 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
34 * following example:
35 *
36 * base + 0x00: Control register, 4 bits per gpio
37 * gpio n: 4 bits starting at (4*n)
38 * 0000 = input, 0001 = output, others mean special-function
39 * base + 0x04: Data register, 1 bit per gpio
40 * bit n: data bit n
41 *
42 * Note, since the data register is one bit per gpio and is at base + 0x4
43 * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
44 * the output.
45*/
46
47static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
48 unsigned int offset)
49{
50 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
51 void __iomem *base = ourchip->base;
52 unsigned long con;
53
54 con = __raw_readl(base + GPIOCON_OFF);
55 con &= ~(0xf << con_4bit_shift(offset));
56 __raw_writel(con, base + GPIOCON_OFF);
57
58 gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
59
60 return 0;
61}
62
63static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
64 unsigned int offset, int value)
65{
66 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
67 void __iomem *base = ourchip->base;
68 unsigned long con;
69 unsigned long dat;
70
71 con = __raw_readl(base + GPIOCON_OFF);
72 con &= ~(0xf << con_4bit_shift(offset));
73 con |= 0x1 << con_4bit_shift(offset);
74
75 dat = __raw_readl(base + GPIODAT_OFF);
76
77 if (value)
78 dat |= 1 << offset;
79 else
80 dat &= ~(1 << offset);
81
82 __raw_writel(dat, base + GPIODAT_OFF);
83 __raw_writel(con, base + GPIOCON_OFF);
84 __raw_writel(dat, base + GPIODAT_OFF);
85
86 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
87
88 return 0;
89}
90
91/* The next set of routines are for the case where the GPIO configuration
92 * registers are 4 bits per GPIO but there is more than one register (the
93 * bank has more than 8 GPIOs.
94 *
95 * This case is the similar to the 4 bit case, but the registers are as
96 * follows:
97 *
98 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
99 * gpio n: 4 bits starting at (4*n)
100 * 0000 = input, 0001 = output, others mean special-function
101 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
102 * gpio n: 4 bits starting at (4*n)
103 * 0000 = input, 0001 = output, others mean special-function
104 * base + 0x08: Data register, 1 bit per gpio
105 * bit n: data bit n
106 *
107 * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we
108 * store the 'base + 0x4' address so that these routines see the data
109 * register at ourchip->base + 0x04.
110 */
111
112static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
113 unsigned int offset)
114{
115 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
116 void __iomem *base = ourchip->base;
117 void __iomem *regcon = base;
118 unsigned long con;
119
120 if (offset > 7)
121 offset -= 8;
122 else
123 regcon -= 4;
124
125 con = __raw_readl(regcon);
126 con &= ~(0xf << con_4bit_shift(offset));
127 __raw_writel(con, regcon);
128
129 gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
130
131 return 0;
132}
133
134static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
135 unsigned int offset, int value)
136{
137 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
138 void __iomem *base = ourchip->base;
139 void __iomem *regcon = base;
140 unsigned long con;
141 unsigned long dat;
142 unsigned con_offset = offset;
143
144 if (con_offset > 7)
145 con_offset -= 8;
146 else
147 regcon -= 4;
148
149 con = __raw_readl(regcon);
150 con &= ~(0xf << con_4bit_shift(con_offset));
151 con |= 0x1 << con_4bit_shift(con_offset);
152
153 dat = __raw_readl(base + GPIODAT_OFF);
154
155 if (value)
156 dat |= 1 << offset;
157 else
158 dat &= ~(1 << offset);
159
160 __raw_writel(dat, base + GPIODAT_OFF);
161 __raw_writel(con, regcon);
162 __raw_writel(dat, base + GPIODAT_OFF);
163
164 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
165
166 return 0;
167}
168
169void __init samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
170{
171 chip->chip.direction_input = samsung_gpiolib_4bit_input;
172 chip->chip.direction_output = samsung_gpiolib_4bit_output;
173 chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
174}
175
176void __init samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
177{
178 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
179 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
180 chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
181}
182
183void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
184 int nr_chips)
185{
186 for (; nr_chips > 0; nr_chips--, chip++) {
187 samsung_gpiolib_add_4bit(chip);
188 s3c_gpiolib_add(chip);
189 }
190}
191
192void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
193 int nr_chips)
194{
195 for (; nr_chips > 0; nr_chips--, chip++) {
196 samsung_gpiolib_add_4bit2(chip);
197 s3c_gpiolib_add(chip);
198 }
199}
200
201void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
202 int nr_chips)
203{
204 for (; nr_chips > 0; nr_chips--, chip++)
205 s3c_gpiolib_add(chip);
206}
diff --git a/drivers/gpio/gpio-s5pc100.c b/drivers/gpio/gpio-s5pc100.c
new file mode 100644
index 000000000000..2842394b28b5
--- /dev/null
+++ b/drivers/gpio/gpio-s5pc100.c
@@ -0,0 +1,355 @@
1/* linux/arch/arm/mach-s5pc100/gpiolib.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2009 Samsung Electronics Co
7 * Kyungmin Park <kyungmin.park@samsung.com>
8 *
9 * S5PC100 - GPIOlib support
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/irq.h>
18#include <linux/io.h>
19#include <linux/gpio.h>
20
21#include <mach/map.h>
22#include <mach/regs-gpio.h>
23
24#include <plat/gpio-core.h>
25#include <plat/gpio-cfg.h>
26#include <plat/gpio-cfg-helpers.h>
27
28/* S5PC100 GPIO bank summary:
29 *
30 * Bank GPIOs Style INT Type
31 * A0 8 4Bit GPIO_INT0
32 * A1 5 4Bit GPIO_INT1
33 * B 8 4Bit GPIO_INT2
34 * C 5 4Bit GPIO_INT3
35 * D 7 4Bit GPIO_INT4
36 * E0 8 4Bit GPIO_INT5
37 * E1 6 4Bit GPIO_INT6
38 * F0 8 4Bit GPIO_INT7
39 * F1 8 4Bit GPIO_INT8
40 * F2 8 4Bit GPIO_INT9
41 * F3 4 4Bit GPIO_INT10
42 * G0 8 4Bit GPIO_INT11
43 * G1 3 4Bit GPIO_INT12
44 * G2 7 4Bit GPIO_INT13
45 * G3 7 4Bit GPIO_INT14
46 * H0 8 4Bit WKUP_INT
47 * H1 8 4Bit WKUP_INT
48 * H2 8 4Bit WKUP_INT
49 * H3 8 4Bit WKUP_INT
50 * I 8 4Bit GPIO_INT15
51 * J0 8 4Bit GPIO_INT16
52 * J1 5 4Bit GPIO_INT17
53 * J2 8 4Bit GPIO_INT18
54 * J3 8 4Bit GPIO_INT19
55 * J4 4 4Bit GPIO_INT20
56 * K0 8 4Bit None
57 * K1 6 4Bit None
58 * K2 8 4Bit None
59 * K3 8 4Bit None
60 * L0 8 4Bit None
61 * L1 8 4Bit None
62 * L2 8 4Bit None
63 * L3 8 4Bit None
64 */
65
66static struct s3c_gpio_cfg gpio_cfg = {
67 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
68 .set_pull = s3c_gpio_setpull_updown,
69 .get_pull = s3c_gpio_getpull_updown,
70};
71
72static struct s3c_gpio_cfg gpio_cfg_eint = {
73 .cfg_eint = 0xf,
74 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
75 .set_pull = s3c_gpio_setpull_updown,
76 .get_pull = s3c_gpio_getpull_updown,
77};
78
79static struct s3c_gpio_cfg gpio_cfg_noint = {
80 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
81 .set_pull = s3c_gpio_setpull_updown,
82 .get_pull = s3c_gpio_getpull_updown,
83};
84
85/*
86 * GPIO bank's base address given the index of the bank in the
87 * list of all gpio banks.
88 */
89#define S5PC100_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20))
90
91/*
92 * Following are the gpio banks in S5PC100.
93 *
94 * The 'config' member when left to NULL, is initialized to the default
95 * structure gpio_cfg in the init function below.
96 *
97 * The 'base' member is also initialized in the init function below.
98 * Note: The initialization of 'base' member of s3c_gpio_chip structure
99 * uses the above macro and depends on the banks being listed in order here.
100 */
101static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
102 {
103 .chip = {
104 .base = S5PC100_GPA0(0),
105 .ngpio = S5PC100_GPIO_A0_NR,
106 .label = "GPA0",
107 },
108 }, {
109 .chip = {
110 .base = S5PC100_GPA1(0),
111 .ngpio = S5PC100_GPIO_A1_NR,
112 .label = "GPA1",
113 },
114 }, {
115 .chip = {
116 .base = S5PC100_GPB(0),
117 .ngpio = S5PC100_GPIO_B_NR,
118 .label = "GPB",
119 },
120 }, {
121 .chip = {
122 .base = S5PC100_GPC(0),
123 .ngpio = S5PC100_GPIO_C_NR,
124 .label = "GPC",
125 },
126 }, {
127 .chip = {
128 .base = S5PC100_GPD(0),
129 .ngpio = S5PC100_GPIO_D_NR,
130 .label = "GPD",
131 },
132 }, {
133 .chip = {
134 .base = S5PC100_GPE0(0),
135 .ngpio = S5PC100_GPIO_E0_NR,
136 .label = "GPE0",
137 },
138 }, {
139 .chip = {
140 .base = S5PC100_GPE1(0),
141 .ngpio = S5PC100_GPIO_E1_NR,
142 .label = "GPE1",
143 },
144 }, {
145 .chip = {
146 .base = S5PC100_GPF0(0),
147 .ngpio = S5PC100_GPIO_F0_NR,
148 .label = "GPF0",
149 },
150 }, {
151 .chip = {
152 .base = S5PC100_GPF1(0),
153 .ngpio = S5PC100_GPIO_F1_NR,
154 .label = "GPF1",
155 },
156 }, {
157 .chip = {
158 .base = S5PC100_GPF2(0),
159 .ngpio = S5PC100_GPIO_F2_NR,
160 .label = "GPF2",
161 },
162 }, {
163 .chip = {
164 .base = S5PC100_GPF3(0),
165 .ngpio = S5PC100_GPIO_F3_NR,
166 .label = "GPF3",
167 },
168 }, {
169 .chip = {
170 .base = S5PC100_GPG0(0),
171 .ngpio = S5PC100_GPIO_G0_NR,
172 .label = "GPG0",
173 },
174 }, {
175 .chip = {
176 .base = S5PC100_GPG1(0),
177 .ngpio = S5PC100_GPIO_G1_NR,
178 .label = "GPG1",
179 },
180 }, {
181 .chip = {
182 .base = S5PC100_GPG2(0),
183 .ngpio = S5PC100_GPIO_G2_NR,
184 .label = "GPG2",
185 },
186 }, {
187 .chip = {
188 .base = S5PC100_GPG3(0),
189 .ngpio = S5PC100_GPIO_G3_NR,
190 .label = "GPG3",
191 },
192 }, {
193 .chip = {
194 .base = S5PC100_GPI(0),
195 .ngpio = S5PC100_GPIO_I_NR,
196 .label = "GPI",
197 },
198 }, {
199 .chip = {
200 .base = S5PC100_GPJ0(0),
201 .ngpio = S5PC100_GPIO_J0_NR,
202 .label = "GPJ0",
203 },
204 }, {
205 .chip = {
206 .base = S5PC100_GPJ1(0),
207 .ngpio = S5PC100_GPIO_J1_NR,
208 .label = "GPJ1",
209 },
210 }, {
211 .chip = {
212 .base = S5PC100_GPJ2(0),
213 .ngpio = S5PC100_GPIO_J2_NR,
214 .label = "GPJ2",
215 },
216 }, {
217 .chip = {
218 .base = S5PC100_GPJ3(0),
219 .ngpio = S5PC100_GPIO_J3_NR,
220 .label = "GPJ3",
221 },
222 }, {
223 .chip = {
224 .base = S5PC100_GPJ4(0),
225 .ngpio = S5PC100_GPIO_J4_NR,
226 .label = "GPJ4",
227 },
228 }, {
229 .config = &gpio_cfg_noint,
230 .chip = {
231 .base = S5PC100_GPK0(0),
232 .ngpio = S5PC100_GPIO_K0_NR,
233 .label = "GPK0",
234 },
235 }, {
236 .config = &gpio_cfg_noint,
237 .chip = {
238 .base = S5PC100_GPK1(0),
239 .ngpio = S5PC100_GPIO_K1_NR,
240 .label = "GPK1",
241 },
242 }, {
243 .config = &gpio_cfg_noint,
244 .chip = {
245 .base = S5PC100_GPK2(0),
246 .ngpio = S5PC100_GPIO_K2_NR,
247 .label = "GPK2",
248 },
249 }, {
250 .config = &gpio_cfg_noint,
251 .chip = {
252 .base = S5PC100_GPK3(0),
253 .ngpio = S5PC100_GPIO_K3_NR,
254 .label = "GPK3",
255 },
256 }, {
257 .config = &gpio_cfg_noint,
258 .chip = {
259 .base = S5PC100_GPL0(0),
260 .ngpio = S5PC100_GPIO_L0_NR,
261 .label = "GPL0",
262 },
263 }, {
264 .config = &gpio_cfg_noint,
265 .chip = {
266 .base = S5PC100_GPL1(0),
267 .ngpio = S5PC100_GPIO_L1_NR,
268 .label = "GPL1",
269 },
270 }, {
271 .config = &gpio_cfg_noint,
272 .chip = {
273 .base = S5PC100_GPL2(0),
274 .ngpio = S5PC100_GPIO_L2_NR,
275 .label = "GPL2",
276 },
277 }, {
278 .config = &gpio_cfg_noint,
279 .chip = {
280 .base = S5PC100_GPL3(0),
281 .ngpio = S5PC100_GPIO_L3_NR,
282 .label = "GPL3",
283 },
284 }, {
285 .config = &gpio_cfg_noint,
286 .chip = {
287 .base = S5PC100_GPL4(0),
288 .ngpio = S5PC100_GPIO_L4_NR,
289 .label = "GPL4",
290 },
291 }, {
292 .base = (S5P_VA_GPIO + 0xC00),
293 .config = &gpio_cfg_eint,
294 .irq_base = IRQ_EINT(0),
295 .chip = {
296 .base = S5PC100_GPH0(0),
297 .ngpio = S5PC100_GPIO_H0_NR,
298 .label = "GPH0",
299 .to_irq = samsung_gpiolib_to_irq,
300 },
301 }, {
302 .base = (S5P_VA_GPIO + 0xC20),
303 .config = &gpio_cfg_eint,
304 .irq_base = IRQ_EINT(8),
305 .chip = {
306 .base = S5PC100_GPH1(0),
307 .ngpio = S5PC100_GPIO_H1_NR,
308 .label = "GPH1",
309 .to_irq = samsung_gpiolib_to_irq,
310 },
311 }, {
312 .base = (S5P_VA_GPIO + 0xC40),
313 .config = &gpio_cfg_eint,
314 .irq_base = IRQ_EINT(16),
315 .chip = {
316 .base = S5PC100_GPH2(0),
317 .ngpio = S5PC100_GPIO_H2_NR,
318 .label = "GPH2",
319 .to_irq = samsung_gpiolib_to_irq,
320 },
321 }, {
322 .base = (S5P_VA_GPIO + 0xC60),
323 .config = &gpio_cfg_eint,
324 .irq_base = IRQ_EINT(24),
325 .chip = {
326 .base = S5PC100_GPH3(0),
327 .ngpio = S5PC100_GPIO_H3_NR,
328 .label = "GPH3",
329 .to_irq = samsung_gpiolib_to_irq,
330 },
331 },
332};
333
334static __init int s5pc100_gpiolib_init(void)
335{
336 struct s3c_gpio_chip *chip = s5pc100_gpio_chips;
337 int nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
338 int gpioint_group = 0;
339 int i;
340
341 for (i = 0; i < nr_chips; i++, chip++) {
342 if (chip->config == NULL) {
343 chip->config = &gpio_cfg;
344 chip->group = gpioint_group++;
345 }
346 if (chip->base == NULL)
347 chip->base = S5PC100_BANK_BASE(i);
348 }
349
350 samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips);
351 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
352
353 return 0;
354}
355core_initcall(s5pc100_gpiolib_init);
diff --git a/drivers/gpio/gpio-s5pv210.c b/drivers/gpio/gpio-s5pv210.c
new file mode 100644
index 000000000000..1ba20a703e05
--- /dev/null
+++ b/drivers/gpio/gpio-s5pv210.c
@@ -0,0 +1,288 @@
1/* linux/arch/arm/mach-s5pv210/gpiolib.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17#include <plat/gpio-core.h>
18#include <plat/gpio-cfg.h>
19#include <plat/gpio-cfg-helpers.h>
20#include <mach/map.h>
21
22static struct s3c_gpio_cfg gpio_cfg = {
23 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
24 .set_pull = s3c_gpio_setpull_updown,
25 .get_pull = s3c_gpio_getpull_updown,
26};
27
28static struct s3c_gpio_cfg gpio_cfg_noint = {
29 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
30 .set_pull = s3c_gpio_setpull_updown,
31 .get_pull = s3c_gpio_getpull_updown,
32};
33
34/* GPIO bank's base address given the index of the bank in the
35 * list of all gpio banks.
36 */
37#define S5PV210_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20))
38
39/*
40 * Following are the gpio banks in v210.
41 *
42 * The 'config' member when left to NULL, is initialized to the default
43 * structure gpio_cfg in the init function below.
44 *
45 * The 'base' member is also initialized in the init function below.
46 * Note: The initialization of 'base' member of s3c_gpio_chip structure
47 * uses the above macro and depends on the banks being listed in order here.
48 */
49static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
50 {
51 .chip = {
52 .base = S5PV210_GPA0(0),
53 .ngpio = S5PV210_GPIO_A0_NR,
54 .label = "GPA0",
55 },
56 }, {
57 .chip = {
58 .base = S5PV210_GPA1(0),
59 .ngpio = S5PV210_GPIO_A1_NR,
60 .label = "GPA1",
61 },
62 }, {
63 .chip = {
64 .base = S5PV210_GPB(0),
65 .ngpio = S5PV210_GPIO_B_NR,
66 .label = "GPB",
67 },
68 }, {
69 .chip = {
70 .base = S5PV210_GPC0(0),
71 .ngpio = S5PV210_GPIO_C0_NR,
72 .label = "GPC0",
73 },
74 }, {
75 .chip = {
76 .base = S5PV210_GPC1(0),
77 .ngpio = S5PV210_GPIO_C1_NR,
78 .label = "GPC1",
79 },
80 }, {
81 .chip = {
82 .base = S5PV210_GPD0(0),
83 .ngpio = S5PV210_GPIO_D0_NR,
84 .label = "GPD0",
85 },
86 }, {
87 .chip = {
88 .base = S5PV210_GPD1(0),
89 .ngpio = S5PV210_GPIO_D1_NR,
90 .label = "GPD1",
91 },
92 }, {
93 .chip = {
94 .base = S5PV210_GPE0(0),
95 .ngpio = S5PV210_GPIO_E0_NR,
96 .label = "GPE0",
97 },
98 }, {
99 .chip = {
100 .base = S5PV210_GPE1(0),
101 .ngpio = S5PV210_GPIO_E1_NR,
102 .label = "GPE1",
103 },
104 }, {
105 .chip = {
106 .base = S5PV210_GPF0(0),
107 .ngpio = S5PV210_GPIO_F0_NR,
108 .label = "GPF0",
109 },
110 }, {
111 .chip = {
112 .base = S5PV210_GPF1(0),
113 .ngpio = S5PV210_GPIO_F1_NR,
114 .label = "GPF1",
115 },
116 }, {
117 .chip = {
118 .base = S5PV210_GPF2(0),
119 .ngpio = S5PV210_GPIO_F2_NR,
120 .label = "GPF2",
121 },
122 }, {
123 .chip = {
124 .base = S5PV210_GPF3(0),
125 .ngpio = S5PV210_GPIO_F3_NR,
126 .label = "GPF3",
127 },
128 }, {
129 .chip = {
130 .base = S5PV210_GPG0(0),
131 .ngpio = S5PV210_GPIO_G0_NR,
132 .label = "GPG0",
133 },
134 }, {
135 .chip = {
136 .base = S5PV210_GPG1(0),
137 .ngpio = S5PV210_GPIO_G1_NR,
138 .label = "GPG1",
139 },
140 }, {
141 .chip = {
142 .base = S5PV210_GPG2(0),
143 .ngpio = S5PV210_GPIO_G2_NR,
144 .label = "GPG2",
145 },
146 }, {
147 .chip = {
148 .base = S5PV210_GPG3(0),
149 .ngpio = S5PV210_GPIO_G3_NR,
150 .label = "GPG3",
151 },
152 }, {
153 .config = &gpio_cfg_noint,
154 .chip = {
155 .base = S5PV210_GPI(0),
156 .ngpio = S5PV210_GPIO_I_NR,
157 .label = "GPI",
158 },
159 }, {
160 .chip = {
161 .base = S5PV210_GPJ0(0),
162 .ngpio = S5PV210_GPIO_J0_NR,
163 .label = "GPJ0",
164 },
165 }, {
166 .chip = {
167 .base = S5PV210_GPJ1(0),
168 .ngpio = S5PV210_GPIO_J1_NR,
169 .label = "GPJ1",
170 },
171 }, {
172 .chip = {
173 .base = S5PV210_GPJ2(0),
174 .ngpio = S5PV210_GPIO_J2_NR,
175 .label = "GPJ2",
176 },
177 }, {
178 .chip = {
179 .base = S5PV210_GPJ3(0),
180 .ngpio = S5PV210_GPIO_J3_NR,
181 .label = "GPJ3",
182 },
183 }, {
184 .chip = {
185 .base = S5PV210_GPJ4(0),
186 .ngpio = S5PV210_GPIO_J4_NR,
187 .label = "GPJ4",
188 },
189 }, {
190 .config = &gpio_cfg_noint,
191 .chip = {
192 .base = S5PV210_MP01(0),
193 .ngpio = S5PV210_GPIO_MP01_NR,
194 .label = "MP01",
195 },
196 }, {
197 .config = &gpio_cfg_noint,
198 .chip = {
199 .base = S5PV210_MP02(0),
200 .ngpio = S5PV210_GPIO_MP02_NR,
201 .label = "MP02",
202 },
203 }, {
204 .config = &gpio_cfg_noint,
205 .chip = {
206 .base = S5PV210_MP03(0),
207 .ngpio = S5PV210_GPIO_MP03_NR,
208 .label = "MP03",
209 },
210 }, {
211 .config = &gpio_cfg_noint,
212 .chip = {
213 .base = S5PV210_MP04(0),
214 .ngpio = S5PV210_GPIO_MP04_NR,
215 .label = "MP04",
216 },
217 }, {
218 .config = &gpio_cfg_noint,
219 .chip = {
220 .base = S5PV210_MP05(0),
221 .ngpio = S5PV210_GPIO_MP05_NR,
222 .label = "MP05",
223 },
224 }, {
225 .base = (S5P_VA_GPIO + 0xC00),
226 .config = &gpio_cfg_noint,
227 .irq_base = IRQ_EINT(0),
228 .chip = {
229 .base = S5PV210_GPH0(0),
230 .ngpio = S5PV210_GPIO_H0_NR,
231 .label = "GPH0",
232 .to_irq = samsung_gpiolib_to_irq,
233 },
234 }, {
235 .base = (S5P_VA_GPIO + 0xC20),
236 .config = &gpio_cfg_noint,
237 .irq_base = IRQ_EINT(8),
238 .chip = {
239 .base = S5PV210_GPH1(0),
240 .ngpio = S5PV210_GPIO_H1_NR,
241 .label = "GPH1",
242 .to_irq = samsung_gpiolib_to_irq,
243 },
244 }, {
245 .base = (S5P_VA_GPIO + 0xC40),
246 .config = &gpio_cfg_noint,
247 .irq_base = IRQ_EINT(16),
248 .chip = {
249 .base = S5PV210_GPH2(0),
250 .ngpio = S5PV210_GPIO_H2_NR,
251 .label = "GPH2",
252 .to_irq = samsung_gpiolib_to_irq,
253 },
254 }, {
255 .base = (S5P_VA_GPIO + 0xC60),
256 .config = &gpio_cfg_noint,
257 .irq_base = IRQ_EINT(24),
258 .chip = {
259 .base = S5PV210_GPH3(0),
260 .ngpio = S5PV210_GPIO_H3_NR,
261 .label = "GPH3",
262 .to_irq = samsung_gpiolib_to_irq,
263 },
264 },
265};
266
267static __init int s5pv210_gpiolib_init(void)
268{
269 struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
270 int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
271 int gpioint_group = 0;
272 int i = 0;
273
274 for (i = 0; i < nr_chips; i++, chip++) {
275 if (chip->config == NULL) {
276 chip->config = &gpio_cfg;
277 chip->group = gpioint_group++;
278 }
279 if (chip->base == NULL)
280 chip->base = S5PV210_BANK_BASE(i);
281 }
282
283 samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips);
284 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
285
286 return 0;
287}
288core_initcall(s5pv210_gpiolib_init);
diff --git a/drivers/gpio/gpio-u300.c b/drivers/gpio/gpio-u300.c
new file mode 100644
index 000000000000..d92790140fe5
--- /dev/null
+++ b/drivers/gpio/gpio-u300.c
@@ -0,0 +1,700 @@
1/*
2 *
3 * arch/arm/mach-u300/gpio.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * U300 GPIO module.
9 * This can driver either of the two basic GPIO cores
10 * available in the U300 platforms:
11 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
12 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
13 * Notice that you also have inline macros in <asm-arch/gpio.h>
14 * Author: Linus Walleij <linus.walleij@stericsson.com>
15 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
16 *
17 */
18#include <linux/module.h>
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/errno.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24#include <linux/err.h>
25#include <linux/platform_device.h>
26#include <linux/gpio.h>
27
28/* Reference to GPIO block clock */
29static struct clk *clk;
30
31/* Memory resource */
32static struct resource *memres;
33static void __iomem *virtbase;
34static struct device *gpiodev;
35
36struct u300_gpio_port {
37 const char *name;
38 int irq;
39 int number;
40};
41
42
43static struct u300_gpio_port gpio_ports[] = {
44 {
45 .name = "gpio0",
46 .number = 0,
47 },
48 {
49 .name = "gpio1",
50 .number = 1,
51 },
52 {
53 .name = "gpio2",
54 .number = 2,
55 },
56#ifdef U300_COH901571_3
57 {
58 .name = "gpio3",
59 .number = 3,
60 },
61 {
62 .name = "gpio4",
63 .number = 4,
64 },
65#ifdef CONFIG_MACH_U300_BS335
66 {
67 .name = "gpio5",
68 .number = 5,
69 },
70 {
71 .name = "gpio6",
72 .number = 6,
73 },
74#endif
75#endif
76
77};
78
79
80#ifdef U300_COH901571_3
81
82/* Default input value */
83#define DEFAULT_OUTPUT_LOW 0
84#define DEFAULT_OUTPUT_HIGH 1
85
86/* GPIO Pull-Up status */
87#define DISABLE_PULL_UP 0
88#define ENABLE_PULL_UP 1
89
90#define GPIO_NOT_USED 0
91#define GPIO_IN 1
92#define GPIO_OUT 2
93
94struct u300_gpio_configuration_data {
95 unsigned char pin_usage;
96 unsigned char default_output_value;
97 unsigned char pull_up;
98};
99
100/* Initial configuration */
101const struct u300_gpio_configuration_data
102u300_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
103#ifdef CONFIG_MACH_U300_BS335
104 /* Port 0, pins 0-7 */
105 {
106 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
107 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
108 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
109 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
110 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
111 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
112 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
113 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
114 },
115 /* Port 1, pins 0-7 */
116 {
117 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
118 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
119 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
120 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
121 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
122 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
123 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
124 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
125 },
126 /* Port 2, pins 0-7 */
127 {
128 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
129 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
130 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
131 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
132 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
133 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
134 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
135 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
136 },
137 /* Port 3, pins 0-7 */
138 {
139 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
140 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
141 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
142 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
143 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
144 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
145 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
146 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
147 },
148 /* Port 4, pins 0-7 */
149 {
150 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
151 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
152 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
153 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
154 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
155 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
156 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
157 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
158 },
159 /* Port 5, pins 0-7 */
160 {
161 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
162 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
163 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
164 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
165 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
166 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
167 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
168 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
169 },
170 /* Port 6, pind 0-7 */
171 {
172 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
173 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
174 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
175 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
176 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
177 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
178 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
179 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
180 }
181#endif
182
183#ifdef CONFIG_MACH_U300_BS365
184 /* Port 0, pins 0-7 */
185 {
186 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
187 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
188 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
189 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
190 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
191 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
192 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
193 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
194 },
195 /* Port 1, pins 0-7 */
196 {
197 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
198 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
199 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
200 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
201 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
202 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
203 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
204 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
205 },
206 /* Port 2, pins 0-7 */
207 {
208 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
209 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
210 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
211 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
212 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
213 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
214 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
215 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
216 },
217 /* Port 3, pins 0-7 */
218 {
219 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
220 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
221 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
222 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
223 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
224 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
225 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
226 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
227 },
228 /* Port 4, pins 0-7 */
229 {
230 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
231 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
232 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
233 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
234 /* These 4 pins doesn't exist on DB3210 */
235 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
236 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
237 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
238 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
239 }
240#endif
241};
242#endif
243
244
245/* No users == we can power down GPIO */
246static int gpio_users;
247
248struct gpio_struct {
249 int (*callback)(void *);
250 void *data;
251 int users;
252};
253
254static struct gpio_struct gpio_pin[U300_GPIO_MAX];
255
256/*
257 * Let drivers register callback in order to get notified when there is
258 * an interrupt on the gpio pin
259 */
260int gpio_register_callback(unsigned gpio, int (*func)(void *arg), void *data)
261{
262 if (gpio_pin[gpio].callback)
263 dev_warn(gpiodev, "%s: WARNING: callback already "
264 "registered for gpio pin#%d\n", __func__, gpio);
265 gpio_pin[gpio].callback = func;
266 gpio_pin[gpio].data = data;
267
268 return 0;
269}
270EXPORT_SYMBOL(gpio_register_callback);
271
272int gpio_unregister_callback(unsigned gpio)
273{
274 if (!gpio_pin[gpio].callback)
275 dev_warn(gpiodev, "%s: WARNING: callback already "
276 "unregistered for gpio pin#%d\n", __func__, gpio);
277 gpio_pin[gpio].callback = NULL;
278 gpio_pin[gpio].data = NULL;
279
280 return 0;
281}
282EXPORT_SYMBOL(gpio_unregister_callback);
283
284/* Non-zero means valid */
285int gpio_is_valid(int number)
286{
287 if (number >= 0 &&
288 number < (U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT))
289 return 1;
290 return 0;
291}
292EXPORT_SYMBOL(gpio_is_valid);
293
294int gpio_request(unsigned gpio, const char *label)
295{
296 if (gpio_pin[gpio].users)
297 return -EINVAL;
298 else
299 gpio_pin[gpio].users++;
300
301 gpio_users++;
302
303 return 0;
304}
305EXPORT_SYMBOL(gpio_request);
306
307void gpio_free(unsigned gpio)
308{
309 gpio_users--;
310 gpio_pin[gpio].users--;
311 if (unlikely(gpio_pin[gpio].users < 0)) {
312 dev_warn(gpiodev, "warning: gpio#%d release mismatch\n",
313 gpio);
314 gpio_pin[gpio].users = 0;
315 }
316
317 return;
318}
319EXPORT_SYMBOL(gpio_free);
320
321/* This returns zero or nonzero */
322int gpio_get_value(unsigned gpio)
323{
324 return readl(virtbase + U300_GPIO_PXPDIR +
325 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) & (1 << (gpio & 0x07));
326}
327EXPORT_SYMBOL(gpio_get_value);
328
329/*
330 * We hope that the compiler will optimize away the unused branch
331 * in case "value" is a constant
332 */
333void gpio_set_value(unsigned gpio, int value)
334{
335 u32 val;
336 unsigned long flags;
337
338 local_irq_save(flags);
339 if (value) {
340 /* set */
341 val = readl(virtbase + U300_GPIO_PXPDOR +
342 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
343 & (1 << (gpio & 0x07));
344 writel(val | (1 << (gpio & 0x07)), virtbase +
345 U300_GPIO_PXPDOR +
346 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
347 } else {
348 /* clear */
349 val = readl(virtbase + U300_GPIO_PXPDOR +
350 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
351 & (1 << (gpio & 0x07));
352 writel(val & ~(1 << (gpio & 0x07)), virtbase +
353 U300_GPIO_PXPDOR +
354 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
355 }
356 local_irq_restore(flags);
357}
358EXPORT_SYMBOL(gpio_set_value);
359
360int gpio_direction_input(unsigned gpio)
361{
362 unsigned long flags;
363 u32 val;
364
365 if (gpio > U300_GPIO_MAX)
366 return -EINVAL;
367
368 local_irq_save(flags);
369 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
370 U300_GPIO_PORTX_SPACING);
371 /* Mask out this pin*/
372 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
373 /* This is not needed since it sets the bits to zero.*/
374 /* val |= (U300_GPIO_PXPCR_PIN_MODE_INPUT << (gpio*2)); */
375 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
376 U300_GPIO_PORTX_SPACING);
377 local_irq_restore(flags);
378 return 0;
379}
380EXPORT_SYMBOL(gpio_direction_input);
381
382int gpio_direction_output(unsigned gpio, int value)
383{
384 unsigned long flags;
385 u32 val;
386
387 if (gpio > U300_GPIO_MAX)
388 return -EINVAL;
389
390 local_irq_save(flags);
391 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
392 U300_GPIO_PORTX_SPACING);
393 /* Mask out this pin */
394 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
395 /*
396 * FIXME: configure for push/pull, open drain or open source per pin
397 * in setup. The current driver will only support push/pull.
398 */
399 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
400 << ((gpio & 0x07) << 1));
401 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
402 U300_GPIO_PORTX_SPACING);
403 gpio_set_value(gpio, value);
404 local_irq_restore(flags);
405 return 0;
406}
407EXPORT_SYMBOL(gpio_direction_output);
408
409/*
410 * Enable an IRQ, edge is rising edge (!= 0) or falling edge (==0).
411 */
412void enable_irq_on_gpio_pin(unsigned gpio, int edge)
413{
414 u32 val;
415 unsigned long flags;
416 local_irq_save(flags);
417
418 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
419 U300_GPIO_PORTX_SPACING);
420 val |= (1 << (gpio & 0x07));
421 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
422 U300_GPIO_PORTX_SPACING);
423 val = readl(virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
424 U300_GPIO_PORTX_SPACING);
425 if (edge)
426 val |= (1 << (gpio & 0x07));
427 else
428 val &= ~(1 << (gpio & 0x07));
429 writel(val, virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
430 U300_GPIO_PORTX_SPACING);
431 local_irq_restore(flags);
432}
433EXPORT_SYMBOL(enable_irq_on_gpio_pin);
434
435void disable_irq_on_gpio_pin(unsigned gpio)
436{
437 u32 val;
438 unsigned long flags;
439
440 local_irq_save(flags);
441 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
442 U300_GPIO_PORTX_SPACING);
443 val &= ~(1 << (gpio & 0x07));
444 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
445 U300_GPIO_PORTX_SPACING);
446 local_irq_restore(flags);
447}
448EXPORT_SYMBOL(disable_irq_on_gpio_pin);
449
450/* Enable (value == 0) or disable (value == 1) internal pullup */
451void gpio_pullup(unsigned gpio, int value)
452{
453 u32 val;
454 unsigned long flags;
455
456 local_irq_save(flags);
457 if (value) {
458 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
459 U300_GPIO_PORTX_SPACING);
460 writel(val | (1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
461 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
462 } else {
463 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
464 U300_GPIO_PORTX_SPACING);
465 writel(val & ~(1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
466 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
467 }
468 local_irq_restore(flags);
469}
470EXPORT_SYMBOL(gpio_pullup);
471
472static irqreturn_t gpio_irq_handler(int irq, void *dev_id)
473{
474 struct u300_gpio_port *port = dev_id;
475 u32 val;
476 int pin;
477
478 /* Read event register */
479 val = readl(virtbase + U300_GPIO_PXIEV + port->number *
480 U300_GPIO_PORTX_SPACING);
481 /* Mask with enable register */
482 val &= readl(virtbase + U300_GPIO_PXIEV + port->number *
483 U300_GPIO_PORTX_SPACING);
484 /* Mask relevant bits */
485 val &= U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK;
486 /* ACK IRQ (clear event) */
487 writel(val, virtbase + U300_GPIO_PXIEV + port->number *
488 U300_GPIO_PORTX_SPACING);
489 /* Print message */
490 while (val != 0) {
491 unsigned gpio;
492
493 pin = __ffs(val);
494 /* mask off this pin */
495 val &= ~(1 << pin);
496 gpio = (port->number << 3) + pin;
497
498 if (gpio_pin[gpio].callback)
499 (void)gpio_pin[gpio].callback(gpio_pin[gpio].data);
500 else
501 dev_dbg(gpiodev, "stray GPIO IRQ on line %d\n",
502 gpio);
503 }
504 return IRQ_HANDLED;
505}
506
507static void gpio_set_initial_values(void)
508{
509#ifdef U300_COH901571_3
510 int i, j;
511 unsigned long flags;
512 u32 val;
513
514 /* Write default values to all pins */
515 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
516 val = 0;
517 for (j = 0; j < 8; j++)
518 val |= (u32) (u300_gpio_config[i][j].default_output_value != DEFAULT_OUTPUT_LOW) << j;
519 local_irq_save(flags);
520 writel(val, virtbase + U300_GPIO_PXPDOR + i * U300_GPIO_PORTX_SPACING);
521 local_irq_restore(flags);
522 }
523
524 /*
525 * Put all pins that are set to either 'GPIO_OUT' or 'GPIO_NOT_USED'
526 * to output and 'GPIO_IN' to input for each port. And initialize
527 * default value on outputs.
528 */
529 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
530 for (j = 0; j < U300_GPIO_PINS_PER_PORT; j++) {
531 local_irq_save(flags);
532 val = readl(virtbase + U300_GPIO_PXPCR +
533 i * U300_GPIO_PORTX_SPACING);
534 /* Mask out this pin */
535 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << (j << 1));
536
537 if (u300_gpio_config[i][j].pin_usage != GPIO_IN)
538 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL << (j << 1));
539 writel(val, virtbase + U300_GPIO_PXPCR +
540 i * U300_GPIO_PORTX_SPACING);
541 local_irq_restore(flags);
542 }
543 }
544
545 /* Enable or disable the internal pull-ups in the GPIO ASIC block */
546 for (i = 0; i < U300_GPIO_MAX; i++) {
547 val = 0;
548 for (j = 0; j < 8; j++)
549 val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP) << j);
550 local_irq_save(flags);
551 writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING);
552 local_irq_restore(flags);
553 }
554#endif
555}
556
557static int __init gpio_probe(struct platform_device *pdev)
558{
559 u32 val;
560 int err = 0;
561 int i;
562 int num_irqs;
563
564 gpiodev = &pdev->dev;
565 memset(gpio_pin, 0, sizeof(gpio_pin));
566
567 /* Get GPIO clock */
568 clk = clk_get(&pdev->dev, NULL);
569 if (IS_ERR(clk)) {
570 err = PTR_ERR(clk);
571 dev_err(gpiodev, "could not get GPIO clock\n");
572 goto err_no_clk;
573 }
574 err = clk_enable(clk);
575 if (err) {
576 dev_err(gpiodev, "could not enable GPIO clock\n");
577 goto err_no_clk_enable;
578 }
579
580 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
581 if (!memres)
582 goto err_no_resource;
583
584 if (request_mem_region(memres->start, memres->end - memres->start, "GPIO Controller")
585 == NULL) {
586 err = -ENODEV;
587 goto err_no_ioregion;
588 }
589
590 virtbase = ioremap(memres->start, resource_size(memres));
591 if (!virtbase) {
592 err = -ENOMEM;
593 goto err_no_ioremap;
594 }
595 dev_info(gpiodev, "remapped 0x%08x to %p\n",
596 memres->start, virtbase);
597
598#ifdef U300_COH901335
599 dev_info(gpiodev, "initializing GPIO Controller COH 901 335\n");
600 /* Turn on the GPIO block */
601 writel(U300_GPIO_CR_BLOCK_CLOCK_ENABLE, virtbase + U300_GPIO_CR);
602#endif
603
604#ifdef U300_COH901571_3
605 dev_info(gpiodev, "initializing GPIO Controller COH 901 571/3\n");
606 val = readl(virtbase + U300_GPIO_CR);
607 dev_info(gpiodev, "COH901571/3 block version: %d, " \
608 "number of cores: %d\n",
609 ((val & 0x0000FE00) >> 9),
610 ((val & 0x000001FC) >> 2));
611 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, virtbase + U300_GPIO_CR);
612#endif
613
614 gpio_set_initial_values();
615
616 for (num_irqs = 0 ; num_irqs < U300_GPIO_NUM_PORTS; num_irqs++) {
617
618 gpio_ports[num_irqs].irq =
619 platform_get_irq_byname(pdev,
620 gpio_ports[num_irqs].name);
621
622 err = request_irq(gpio_ports[num_irqs].irq,
623 gpio_irq_handler, IRQF_DISABLED,
624 gpio_ports[num_irqs].name,
625 &gpio_ports[num_irqs]);
626 if (err) {
627 dev_err(gpiodev, "cannot allocate IRQ for %s!\n",
628 gpio_ports[num_irqs].name);
629 goto err_no_irq;
630 }
631 /* Turns off PortX_irq_force */
632 writel(0x0, virtbase + U300_GPIO_PXIFR +
633 num_irqs * U300_GPIO_PORTX_SPACING);
634 }
635
636 return 0;
637
638 err_no_irq:
639 for (i = 0; i < num_irqs; i++)
640 free_irq(gpio_ports[i].irq, &gpio_ports[i]);
641 iounmap(virtbase);
642 err_no_ioremap:
643 release_mem_region(memres->start, memres->end - memres->start);
644 err_no_ioregion:
645 err_no_resource:
646 clk_disable(clk);
647 err_no_clk_enable:
648 clk_put(clk);
649 err_no_clk:
650 dev_info(gpiodev, "module ERROR:%d\n", err);
651 return err;
652}
653
654static int __exit gpio_remove(struct platform_device *pdev)
655{
656 int i;
657
658 /* Turn off the GPIO block */
659 writel(0x00000000U, virtbase + U300_GPIO_CR);
660 for (i = 0 ; i < U300_GPIO_NUM_PORTS; i++)
661 free_irq(gpio_ports[i].irq, &gpio_ports[i]);
662 iounmap(virtbase);
663 release_mem_region(memres->start, memres->end - memres->start);
664 clk_disable(clk);
665 clk_put(clk);
666 return 0;
667}
668
669static struct platform_driver gpio_driver = {
670 .driver = {
671 .name = "u300-gpio",
672 },
673 .remove = __exit_p(gpio_remove),
674};
675
676
677static int __init u300_gpio_init(void)
678{
679 return platform_driver_probe(&gpio_driver, gpio_probe);
680}
681
682static void __exit u300_gpio_exit(void)
683{
684 platform_driver_unregister(&gpio_driver);
685}
686
687arch_initcall(u300_gpio_init);
688module_exit(u300_gpio_exit);
689
690MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
691
692#ifdef U300_COH901571_3
693MODULE_DESCRIPTION("ST-Ericsson AB COH 901 571/3 GPIO driver");
694#endif
695
696#ifdef U300_COH901335
697MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335 GPIO driver");
698#endif
699
700MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 137a8ca67822..a971e3d043ba 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1296,7 +1296,7 @@ EXPORT_SYMBOL_GPL(gpio_request_one);
1296 * @array: array of the 'struct gpio' 1296 * @array: array of the 'struct gpio'
1297 * @num: how many GPIOs in the array 1297 * @num: how many GPIOs in the array
1298 */ 1298 */
1299int gpio_request_array(struct gpio *array, size_t num) 1299int gpio_request_array(const struct gpio *array, size_t num)
1300{ 1300{
1301 int i, err; 1301 int i, err;
1302 1302
@@ -1319,7 +1319,7 @@ EXPORT_SYMBOL_GPL(gpio_request_array);
1319 * @array: array of the 'struct gpio' 1319 * @array: array of the 'struct gpio'
1320 * @num: how many GPIOs in the array 1320 * @num: how many GPIOs in the array
1321 */ 1321 */
1322void gpio_free_array(struct gpio *array, size_t num) 1322void gpio_free_array(const struct gpio *array, size_t num)
1323{ 1323{
1324 while (num--) 1324 while (num--)
1325 gpio_free((array++)->gpio); 1325 gpio_free((array++)->gpio);
diff --git a/drivers/gpio/langwell_gpio.c b/drivers/gpio/langwell_gpio.c
index 1b06f67e1f69..bd6571e0097a 100644
--- a/drivers/gpio/langwell_gpio.c
+++ b/drivers/gpio/langwell_gpio.c
@@ -33,6 +33,7 @@
33#include <linux/io.h> 33#include <linux/io.h>
34#include <linux/gpio.h> 34#include <linux/gpio.h>
35#include <linux/slab.h> 35#include <linux/slab.h>
36#include <linux/pm_runtime.h>
36 37
37/* 38/*
38 * Langwell chip has 64 pins and thus there are 2 32bit registers to control 39 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
@@ -63,6 +64,7 @@ struct lnw_gpio {
63 void *reg_base; 64 void *reg_base;
64 spinlock_t lock; 65 spinlock_t lock;
65 unsigned irq_base; 66 unsigned irq_base;
67 struct pci_dev *pdev;
66}; 68};
67 69
68static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset, 70static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
@@ -104,11 +106,18 @@ static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
104 u32 value; 106 u32 value;
105 unsigned long flags; 107 unsigned long flags;
106 108
109 if (lnw->pdev)
110 pm_runtime_get(&lnw->pdev->dev);
111
107 spin_lock_irqsave(&lnw->lock, flags); 112 spin_lock_irqsave(&lnw->lock, flags);
108 value = readl(gpdr); 113 value = readl(gpdr);
109 value &= ~BIT(offset % 32); 114 value &= ~BIT(offset % 32);
110 writel(value, gpdr); 115 writel(value, gpdr);
111 spin_unlock_irqrestore(&lnw->lock, flags); 116 spin_unlock_irqrestore(&lnw->lock, flags);
117
118 if (lnw->pdev)
119 pm_runtime_put(&lnw->pdev->dev);
120
112 return 0; 121 return 0;
113} 122}
114 123
@@ -120,11 +129,19 @@ static int lnw_gpio_direction_output(struct gpio_chip *chip,
120 unsigned long flags; 129 unsigned long flags;
121 130
122 lnw_gpio_set(chip, offset, value); 131 lnw_gpio_set(chip, offset, value);
132
133 if (lnw->pdev)
134 pm_runtime_get(&lnw->pdev->dev);
135
123 spin_lock_irqsave(&lnw->lock, flags); 136 spin_lock_irqsave(&lnw->lock, flags);
124 value = readl(gpdr); 137 value = readl(gpdr);
125 value |= BIT(offset % 32); 138 value |= BIT(offset % 32);
126 writel(value, gpdr); 139 writel(value, gpdr);
127 spin_unlock_irqrestore(&lnw->lock, flags); 140 spin_unlock_irqrestore(&lnw->lock, flags);
141
142 if (lnw->pdev)
143 pm_runtime_put(&lnw->pdev->dev);
144
128 return 0; 145 return 0;
129} 146}
130 147
@@ -145,6 +162,10 @@ static int lnw_irq_type(struct irq_data *d, unsigned type)
145 162
146 if (gpio >= lnw->chip.ngpio) 163 if (gpio >= lnw->chip.ngpio)
147 return -EINVAL; 164 return -EINVAL;
165
166 if (lnw->pdev)
167 pm_runtime_get(&lnw->pdev->dev);
168
148 spin_lock_irqsave(&lnw->lock, flags); 169 spin_lock_irqsave(&lnw->lock, flags);
149 if (type & IRQ_TYPE_EDGE_RISING) 170 if (type & IRQ_TYPE_EDGE_RISING)
150 value = readl(grer) | BIT(gpio % 32); 171 value = readl(grer) | BIT(gpio % 32);
@@ -159,6 +180,9 @@ static int lnw_irq_type(struct irq_data *d, unsigned type)
159 writel(value, gfer); 180 writel(value, gfer);
160 spin_unlock_irqrestore(&lnw->lock, flags); 181 spin_unlock_irqrestore(&lnw->lock, flags);
161 182
183 if (lnw->pdev)
184 pm_runtime_put(&lnw->pdev->dev);
185
162 return 0; 186 return 0;
163} 187}
164 188
@@ -211,6 +235,39 @@ static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
211 chip->irq_eoi(data); 235 chip->irq_eoi(data);
212} 236}
213 237
238#ifdef CONFIG_PM
239static int lnw_gpio_runtime_resume(struct device *dev)
240{
241 return 0;
242}
243
244static int lnw_gpio_runtime_suspend(struct device *dev)
245{
246 return 0;
247}
248
249static int lnw_gpio_runtime_idle(struct device *dev)
250{
251 int err = pm_schedule_suspend(dev, 500);
252
253 if (!err)
254 return 0;
255
256 return -EBUSY;
257}
258
259#else
260#define lnw_gpio_runtime_suspend NULL
261#define lnw_gpio_runtime_resume NULL
262#define lnw_gpio_runtime_idle NULL
263#endif
264
265static const struct dev_pm_ops lnw_gpio_pm_ops = {
266 .runtime_suspend = lnw_gpio_runtime_suspend,
267 .runtime_resume = lnw_gpio_runtime_resume,
268 .runtime_idle = lnw_gpio_runtime_idle,
269};
270
214static int __devinit lnw_gpio_probe(struct pci_dev *pdev, 271static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
215 const struct pci_device_id *id) 272 const struct pci_device_id *id)
216{ 273{
@@ -270,6 +327,7 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
270 lnw->chip.base = gpio_base; 327 lnw->chip.base = gpio_base;
271 lnw->chip.ngpio = id->driver_data; 328 lnw->chip.ngpio = id->driver_data;
272 lnw->chip.can_sleep = 0; 329 lnw->chip.can_sleep = 0;
330 lnw->pdev = pdev;
273 pci_set_drvdata(pdev, lnw); 331 pci_set_drvdata(pdev, lnw);
274 retval = gpiochip_add(&lnw->chip); 332 retval = gpiochip_add(&lnw->chip);
275 if (retval) { 333 if (retval) {
@@ -285,6 +343,10 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
285 } 343 }
286 344
287 spin_lock_init(&lnw->lock); 345 spin_lock_init(&lnw->lock);
346
347 pm_runtime_put_noidle(&pdev->dev);
348 pm_runtime_allow(&pdev->dev);
349
288 goto done; 350 goto done;
289err5: 351err5:
290 kfree(lnw); 352 kfree(lnw);
@@ -302,6 +364,9 @@ static struct pci_driver lnw_gpio_driver = {
302 .name = "langwell_gpio", 364 .name = "langwell_gpio",
303 .id_table = lnw_gpio_ids, 365 .id_table = lnw_gpio_ids,
304 .probe = lnw_gpio_probe, 366 .probe = lnw_gpio_probe,
367 .driver = {
368 .pm = &lnw_gpio_pm_ops,
369 },
305}; 370};
306 371
307 372
diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c
index 78a843947d82..0451d7ac94ac 100644
--- a/drivers/gpio/pca953x.c
+++ b/drivers/gpio/pca953x.c
@@ -24,33 +24,46 @@
24#include <linux/of_gpio.h> 24#include <linux/of_gpio.h>
25#endif 25#endif
26 26
27#define PCA953X_INPUT 0 27#define PCA953X_INPUT 0
28#define PCA953X_OUTPUT 1 28#define PCA953X_OUTPUT 1
29#define PCA953X_INVERT 2 29#define PCA953X_INVERT 2
30#define PCA953X_DIRECTION 3 30#define PCA953X_DIRECTION 3
31 31
32#define PCA953X_GPIOS 0x00FF 32#define PCA957X_IN 0
33#define PCA953X_INT 0x0100 33#define PCA957X_INVRT 1
34#define PCA957X_BKEN 2
35#define PCA957X_PUPD 3
36#define PCA957X_CFG 4
37#define PCA957X_OUT 5
38#define PCA957X_MSK 6
39#define PCA957X_INTS 7
40
41#define PCA_GPIO_MASK 0x00FF
42#define PCA_INT 0x0100
43#define PCA953X_TYPE 0x1000
44#define PCA957X_TYPE 0x2000
34 45
35static const struct i2c_device_id pca953x_id[] = { 46static const struct i2c_device_id pca953x_id[] = {
36 { "pca9534", 8 | PCA953X_INT, }, 47 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
37 { "pca9535", 16 | PCA953X_INT, }, 48 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
38 { "pca9536", 4, }, 49 { "pca9536", 4 | PCA953X_TYPE, },
39 { "pca9537", 4 | PCA953X_INT, }, 50 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
40 { "pca9538", 8 | PCA953X_INT, }, 51 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
41 { "pca9539", 16 | PCA953X_INT, }, 52 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
42 { "pca9554", 8 | PCA953X_INT, }, 53 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
43 { "pca9555", 16 | PCA953X_INT, }, 54 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
44 { "pca9556", 8, }, 55 { "pca9556", 8 | PCA953X_TYPE, },
45 { "pca9557", 8, }, 56 { "pca9557", 8 | PCA953X_TYPE, },
46 57 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
47 { "max7310", 8, }, 58 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
48 { "max7312", 16 | PCA953X_INT, }, 59
49 { "max7313", 16 | PCA953X_INT, }, 60 { "max7310", 8 | PCA953X_TYPE, },
50 { "max7315", 8 | PCA953X_INT, }, 61 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
51 { "pca6107", 8 | PCA953X_INT, }, 62 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
52 { "tca6408", 8 | PCA953X_INT, }, 63 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
53 { "tca6416", 16 | PCA953X_INT, }, 64 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
65 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
66 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
54 /* NYET: { "tca6424", 24, }, */ 67 /* NYET: { "tca6424", 24, }, */
55 { } 68 { }
56}; 69};
@@ -75,16 +88,32 @@ struct pca953x_chip {
75 struct pca953x_platform_data *dyn_pdata; 88 struct pca953x_platform_data *dyn_pdata;
76 struct gpio_chip gpio_chip; 89 struct gpio_chip gpio_chip;
77 const char *const *names; 90 const char *const *names;
91 int chip_type;
78}; 92};
79 93
80static int pca953x_write_reg(struct pca953x_chip *chip, int reg, uint16_t val) 94static int pca953x_write_reg(struct pca953x_chip *chip, int reg, uint16_t val)
81{ 95{
82 int ret; 96 int ret = 0;
83 97
84 if (chip->gpio_chip.ngpio <= 8) 98 if (chip->gpio_chip.ngpio <= 8)
85 ret = i2c_smbus_write_byte_data(chip->client, reg, val); 99 ret = i2c_smbus_write_byte_data(chip->client, reg, val);
86 else 100 else {
87 ret = i2c_smbus_write_word_data(chip->client, reg << 1, val); 101 switch (chip->chip_type) {
102 case PCA953X_TYPE:
103 ret = i2c_smbus_write_word_data(chip->client,
104 reg << 1, val);
105 break;
106 case PCA957X_TYPE:
107 ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
108 val & 0xff);
109 if (ret < 0)
110 break;
111 ret = i2c_smbus_write_byte_data(chip->client,
112 (reg << 1) + 1,
113 (val & 0xff00) >> 8);
114 break;
115 }
116 }
88 117
89 if (ret < 0) { 118 if (ret < 0) {
90 dev_err(&chip->client->dev, "failed writing register\n"); 119 dev_err(&chip->client->dev, "failed writing register\n");
@@ -116,13 +145,22 @@ static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
116{ 145{
117 struct pca953x_chip *chip; 146 struct pca953x_chip *chip;
118 uint16_t reg_val; 147 uint16_t reg_val;
119 int ret; 148 int ret, offset = 0;
120 149
121 chip = container_of(gc, struct pca953x_chip, gpio_chip); 150 chip = container_of(gc, struct pca953x_chip, gpio_chip);
122 151
123 mutex_lock(&chip->i2c_lock); 152 mutex_lock(&chip->i2c_lock);
124 reg_val = chip->reg_direction | (1u << off); 153 reg_val = chip->reg_direction | (1u << off);
125 ret = pca953x_write_reg(chip, PCA953X_DIRECTION, reg_val); 154
155 switch (chip->chip_type) {
156 case PCA953X_TYPE:
157 offset = PCA953X_DIRECTION;
158 break;
159 case PCA957X_TYPE:
160 offset = PCA957X_CFG;
161 break;
162 }
163 ret = pca953x_write_reg(chip, offset, reg_val);
126 if (ret) 164 if (ret)
127 goto exit; 165 goto exit;
128 166
@@ -138,7 +176,7 @@ static int pca953x_gpio_direction_output(struct gpio_chip *gc,
138{ 176{
139 struct pca953x_chip *chip; 177 struct pca953x_chip *chip;
140 uint16_t reg_val; 178 uint16_t reg_val;
141 int ret; 179 int ret, offset = 0;
142 180
143 chip = container_of(gc, struct pca953x_chip, gpio_chip); 181 chip = container_of(gc, struct pca953x_chip, gpio_chip);
144 182
@@ -149,7 +187,15 @@ static int pca953x_gpio_direction_output(struct gpio_chip *gc,
149 else 187 else
150 reg_val = chip->reg_output & ~(1u << off); 188 reg_val = chip->reg_output & ~(1u << off);
151 189
152 ret = pca953x_write_reg(chip, PCA953X_OUTPUT, reg_val); 190 switch (chip->chip_type) {
191 case PCA953X_TYPE:
192 offset = PCA953X_OUTPUT;
193 break;
194 case PCA957X_TYPE:
195 offset = PCA957X_OUT;
196 break;
197 }
198 ret = pca953x_write_reg(chip, offset, reg_val);
153 if (ret) 199 if (ret)
154 goto exit; 200 goto exit;
155 201
@@ -157,7 +203,15 @@ static int pca953x_gpio_direction_output(struct gpio_chip *gc,
157 203
158 /* then direction */ 204 /* then direction */
159 reg_val = chip->reg_direction & ~(1u << off); 205 reg_val = chip->reg_direction & ~(1u << off);
160 ret = pca953x_write_reg(chip, PCA953X_DIRECTION, reg_val); 206 switch (chip->chip_type) {
207 case PCA953X_TYPE:
208 offset = PCA953X_DIRECTION;
209 break;
210 case PCA957X_TYPE:
211 offset = PCA957X_CFG;
212 break;
213 }
214 ret = pca953x_write_reg(chip, offset, reg_val);
161 if (ret) 215 if (ret)
162 goto exit; 216 goto exit;
163 217
@@ -172,12 +226,20 @@ static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
172{ 226{
173 struct pca953x_chip *chip; 227 struct pca953x_chip *chip;
174 uint16_t reg_val; 228 uint16_t reg_val;
175 int ret; 229 int ret, offset = 0;
176 230
177 chip = container_of(gc, struct pca953x_chip, gpio_chip); 231 chip = container_of(gc, struct pca953x_chip, gpio_chip);
178 232
179 mutex_lock(&chip->i2c_lock); 233 mutex_lock(&chip->i2c_lock);
180 ret = pca953x_read_reg(chip, PCA953X_INPUT, &reg_val); 234 switch (chip->chip_type) {
235 case PCA953X_TYPE:
236 offset = PCA953X_INPUT;
237 break;
238 case PCA957X_TYPE:
239 offset = PCA957X_IN;
240 break;
241 }
242 ret = pca953x_read_reg(chip, offset, &reg_val);
181 mutex_unlock(&chip->i2c_lock); 243 mutex_unlock(&chip->i2c_lock);
182 if (ret < 0) { 244 if (ret < 0) {
183 /* NOTE: diagnostic already emitted; that's all we should 245 /* NOTE: diagnostic already emitted; that's all we should
@@ -194,7 +256,7 @@ static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
194{ 256{
195 struct pca953x_chip *chip; 257 struct pca953x_chip *chip;
196 uint16_t reg_val; 258 uint16_t reg_val;
197 int ret; 259 int ret, offset = 0;
198 260
199 chip = container_of(gc, struct pca953x_chip, gpio_chip); 261 chip = container_of(gc, struct pca953x_chip, gpio_chip);
200 262
@@ -204,7 +266,15 @@ static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
204 else 266 else
205 reg_val = chip->reg_output & ~(1u << off); 267 reg_val = chip->reg_output & ~(1u << off);
206 268
207 ret = pca953x_write_reg(chip, PCA953X_OUTPUT, reg_val); 269 switch (chip->chip_type) {
270 case PCA953X_TYPE:
271 offset = PCA953X_OUTPUT;
272 break;
273 case PCA957X_TYPE:
274 offset = PCA957X_OUT;
275 break;
276 }
277 ret = pca953x_write_reg(chip, offset, reg_val);
208 if (ret) 278 if (ret)
209 goto exit; 279 goto exit;
210 280
@@ -322,9 +392,17 @@ static uint16_t pca953x_irq_pending(struct pca953x_chip *chip)
322 uint16_t old_stat; 392 uint16_t old_stat;
323 uint16_t pending; 393 uint16_t pending;
324 uint16_t trigger; 394 uint16_t trigger;
325 int ret; 395 int ret, offset = 0;
326 396
327 ret = pca953x_read_reg(chip, PCA953X_INPUT, &cur_stat); 397 switch (chip->chip_type) {
398 case PCA953X_TYPE:
399 offset = PCA953X_INPUT;
400 break;
401 case PCA957X_TYPE:
402 offset = PCA957X_IN;
403 break;
404 }
405 ret = pca953x_read_reg(chip, offset, &cur_stat);
328 if (ret) 406 if (ret)
329 return 0; 407 return 0;
330 408
@@ -372,14 +450,21 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
372{ 450{
373 struct i2c_client *client = chip->client; 451 struct i2c_client *client = chip->client;
374 struct pca953x_platform_data *pdata = client->dev.platform_data; 452 struct pca953x_platform_data *pdata = client->dev.platform_data;
375 int ret; 453 int ret, offset = 0;
376 454
377 if (pdata->irq_base != -1 455 if (pdata->irq_base != -1
378 && (id->driver_data & PCA953X_INT)) { 456 && (id->driver_data & PCA_INT)) {
379 int lvl; 457 int lvl;
380 458
381 ret = pca953x_read_reg(chip, PCA953X_INPUT, 459 switch (chip->chip_type) {
382 &chip->irq_stat); 460 case PCA953X_TYPE:
461 offset = PCA953X_INPUT;
462 break;
463 case PCA957X_TYPE:
464 offset = PCA957X_IN;
465 break;
466 }
467 ret = pca953x_read_reg(chip, offset, &chip->irq_stat);
383 if (ret) 468 if (ret)
384 goto out_failed; 469 goto out_failed;
385 470
@@ -439,7 +524,7 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
439 struct i2c_client *client = chip->client; 524 struct i2c_client *client = chip->client;
440 struct pca953x_platform_data *pdata = client->dev.platform_data; 525 struct pca953x_platform_data *pdata = client->dev.platform_data;
441 526
442 if (pdata->irq_base != -1 && (id->driver_data & PCA953X_INT)) 527 if (pdata->irq_base != -1 && (id->driver_data & PCA_INT))
443 dev_warn(&client->dev, "interrupt support not compiled in\n"); 528 dev_warn(&client->dev, "interrupt support not compiled in\n");
444 529
445 return 0; 530 return 0;
@@ -499,12 +584,65 @@ pca953x_get_alt_pdata(struct i2c_client *client)
499} 584}
500#endif 585#endif
501 586
587static int __devinit device_pca953x_init(struct pca953x_chip *chip, int invert)
588{
589 int ret;
590
591 ret = pca953x_read_reg(chip, PCA953X_OUTPUT, &chip->reg_output);
592 if (ret)
593 goto out;
594
595 ret = pca953x_read_reg(chip, PCA953X_DIRECTION,
596 &chip->reg_direction);
597 if (ret)
598 goto out;
599
600 /* set platform specific polarity inversion */
601 ret = pca953x_write_reg(chip, PCA953X_INVERT, invert);
602 if (ret)
603 goto out;
604 return 0;
605out:
606 return ret;
607}
608
609static int __devinit device_pca957x_init(struct pca953x_chip *chip, int invert)
610{
611 int ret;
612 uint16_t val = 0;
613
614 /* Let every port in proper state, that could save power */
615 pca953x_write_reg(chip, PCA957X_PUPD, 0x0);
616 pca953x_write_reg(chip, PCA957X_CFG, 0xffff);
617 pca953x_write_reg(chip, PCA957X_OUT, 0x0);
618
619 ret = pca953x_read_reg(chip, PCA957X_IN, &val);
620 if (ret)
621 goto out;
622 ret = pca953x_read_reg(chip, PCA957X_OUT, &chip->reg_output);
623 if (ret)
624 goto out;
625 ret = pca953x_read_reg(chip, PCA957X_CFG, &chip->reg_direction);
626 if (ret)
627 goto out;
628
629 /* set platform specific polarity inversion */
630 pca953x_write_reg(chip, PCA957X_INVRT, invert);
631
632 /* To enable register 6, 7 to controll pull up and pull down */
633 pca953x_write_reg(chip, PCA957X_BKEN, 0x202);
634
635 return 0;
636out:
637 return ret;
638}
639
502static int __devinit pca953x_probe(struct i2c_client *client, 640static int __devinit pca953x_probe(struct i2c_client *client,
503 const struct i2c_device_id *id) 641 const struct i2c_device_id *id)
504{ 642{
505 struct pca953x_platform_data *pdata; 643 struct pca953x_platform_data *pdata;
506 struct pca953x_chip *chip; 644 struct pca953x_chip *chip;
507 int ret; 645 int ret = 0;
508 646
509 chip = kzalloc(sizeof(struct pca953x_chip), GFP_KERNEL); 647 chip = kzalloc(sizeof(struct pca953x_chip), GFP_KERNEL);
510 if (chip == NULL) 648 if (chip == NULL)
@@ -531,25 +669,20 @@ static int __devinit pca953x_probe(struct i2c_client *client,
531 chip->gpio_start = pdata->gpio_base; 669 chip->gpio_start = pdata->gpio_base;
532 670
533 chip->names = pdata->names; 671 chip->names = pdata->names;
672 chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE);
534 673
535 mutex_init(&chip->i2c_lock); 674 mutex_init(&chip->i2c_lock);
536 675
537 /* initialize cached registers from their original values. 676 /* initialize cached registers from their original values.
538 * we can't share this chip with another i2c master. 677 * we can't share this chip with another i2c master.
539 */ 678 */
540 pca953x_setup_gpio(chip, id->driver_data & PCA953X_GPIOS); 679 pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK);
541 680
542 ret = pca953x_read_reg(chip, PCA953X_OUTPUT, &chip->reg_output); 681 if (chip->chip_type == PCA953X_TYPE)
543 if (ret) 682 device_pca953x_init(chip, pdata->invert);
544 goto out_failed; 683 else if (chip->chip_type == PCA957X_TYPE)
545 684 device_pca957x_init(chip, pdata->invert);
546 ret = pca953x_read_reg(chip, PCA953X_DIRECTION, &chip->reg_direction); 685 else
547 if (ret)
548 goto out_failed;
549
550 /* set platform specific polarity inversion */
551 ret = pca953x_write_reg(chip, PCA953X_INVERT, pdata->invert);
552 if (ret)
553 goto out_failed; 686 goto out_failed;
554 687
555 ret = pca953x_irq_setup(chip, id); 688 ret = pca953x_irq_setup(chip, id);
diff --git a/drivers/gpio/pch_gpio.c b/drivers/gpio/pch_gpio.c
index f970a5f3585e..36919e77c495 100644
--- a/drivers/gpio/pch_gpio.c
+++ b/drivers/gpio/pch_gpio.c
@@ -283,8 +283,10 @@ static int pch_gpio_resume(struct pci_dev *pdev)
283#define pch_gpio_resume NULL 283#define pch_gpio_resume NULL
284#endif 284#endif
285 285
286#define PCI_VENDOR_ID_ROHM 0x10DB
286static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = { 287static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = {
287 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) }, 288 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
289 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
288 { 0, } 290 { 0, }
289}; 291};
290MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id); 292MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 12:24:19 -0500