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authorTomasz Figa <t.figa@samsung.com>2013-08-26 13:35:55 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-08-29 08:40:30 -0400
commit6c56c6cd8031e01719e5a5392571c3be08737434 (patch)
treeb2a2c37872532f69ee06c18d1fe70e4eb569a842 /drivers/gpio
parent655c4e79370d1731c293c47aaf85d4c990a33052 (diff)
gpio: samsung: Drop support for Exynos SoCs
GPIO support on Exynos SoCs is provided by pinctrl-samsung driver, leaving all the support code in gpio-samsung driver unused. This dead code can be safely removed and so it is done by this patch. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/gpio-samsung.c871
1 files changed, 0 insertions, 871 deletions
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index a1392f47bbda..358a21c2d811 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -161,28 +161,6 @@ int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
161 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN); 161 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
162} 162}
163 163
164static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
165 unsigned int off, samsung_gpio_pull_t pull)
166{
167 if (pull == S3C_GPIO_PULL_UP)
168 pull = 3;
169
170 return samsung_gpio_setpull_updown(chip, off, pull);
171}
172
173static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
174 unsigned int off)
175{
176 samsung_gpio_pull_t pull;
177
178 pull = samsung_gpio_getpull_updown(chip, off);
179
180 if (pull == 3)
181 pull = S3C_GPIO_PULL_UP;
182
183 return pull;
184}
185
186/* 164/*
187 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration. 165 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
188 * @chip: The gpio chip that is being configured. 166 * @chip: The gpio chip that is being configured.
@@ -444,15 +422,6 @@ static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
444}; 422};
445#endif 423#endif
446 424
447#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_SOC_EXYNOS5250)
448static struct samsung_gpio_cfg exynos_gpio_cfg = {
449 .set_pull = exynos_gpio_setpull,
450 .get_pull = exynos_gpio_getpull,
451 .set_config = samsung_gpio_setcfg_4bit,
452 .get_config = samsung_gpio_getcfg_4bit,
453};
454#endif
455
456#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) 425#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
457static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = { 426static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
458 .cfg_eint = 0x3, 427 .cfg_eint = 0x3,
@@ -495,15 +464,6 @@ static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
495 .set_config = samsung_gpio_setcfg_2bit, 464 .set_config = samsung_gpio_setcfg_2bit,
496 .get_config = samsung_gpio_getcfg_2bit, 465 .get_config = samsung_gpio_getcfg_2bit,
497 }, 466 },
498 [8] = {
499 .set_pull = exynos_gpio_setpull,
500 .get_pull = exynos_gpio_getpull,
501 },
502 [9] = {
503 .cfg_eint = 0x3,
504 .set_pull = exynos_gpio_setpull,
505 .get_pull = exynos_gpio_getpull,
506 }
507}; 467};
508 468
509/* 469/*
@@ -2115,833 +2075,6 @@ static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
2115#endif 2075#endif
2116}; 2076};
2117 2077
2118/*
2119 * Followings are the gpio banks in EXYNOS SoCs
2120 *
2121 * The 'config' member when left to NULL, is initialized to the default
2122 * structure exynos_gpio_cfg in the init function below.
2123 *
2124 * The 'base' member is also initialized in the init function below.
2125 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2126 * uses the above macro and depends on the banks being listed in order here.
2127 */
2128
2129#ifdef CONFIG_ARCH_EXYNOS4
2130static struct samsung_gpio_chip exynos4_gpios_1[] = {
2131 {
2132 .chip = {
2133 .base = EXYNOS4_GPA0(0),
2134 .ngpio = EXYNOS4_GPIO_A0_NR,
2135 .label = "GPA0",
2136 },
2137 }, {
2138 .chip = {
2139 .base = EXYNOS4_GPA1(0),
2140 .ngpio = EXYNOS4_GPIO_A1_NR,
2141 .label = "GPA1",
2142 },
2143 }, {
2144 .chip = {
2145 .base = EXYNOS4_GPB(0),
2146 .ngpio = EXYNOS4_GPIO_B_NR,
2147 .label = "GPB",
2148 },
2149 }, {
2150 .chip = {
2151 .base = EXYNOS4_GPC0(0),
2152 .ngpio = EXYNOS4_GPIO_C0_NR,
2153 .label = "GPC0",
2154 },
2155 }, {
2156 .chip = {
2157 .base = EXYNOS4_GPC1(0),
2158 .ngpio = EXYNOS4_GPIO_C1_NR,
2159 .label = "GPC1",
2160 },
2161 }, {
2162 .chip = {
2163 .base = EXYNOS4_GPD0(0),
2164 .ngpio = EXYNOS4_GPIO_D0_NR,
2165 .label = "GPD0",
2166 },
2167 }, {
2168 .chip = {
2169 .base = EXYNOS4_GPD1(0),
2170 .ngpio = EXYNOS4_GPIO_D1_NR,
2171 .label = "GPD1",
2172 },
2173 }, {
2174 .chip = {
2175 .base = EXYNOS4_GPE0(0),
2176 .ngpio = EXYNOS4_GPIO_E0_NR,
2177 .label = "GPE0",
2178 },
2179 }, {
2180 .chip = {
2181 .base = EXYNOS4_GPE1(0),
2182 .ngpio = EXYNOS4_GPIO_E1_NR,
2183 .label = "GPE1",
2184 },
2185 }, {
2186 .chip = {
2187 .base = EXYNOS4_GPE2(0),
2188 .ngpio = EXYNOS4_GPIO_E2_NR,
2189 .label = "GPE2",
2190 },
2191 }, {
2192 .chip = {
2193 .base = EXYNOS4_GPE3(0),
2194 .ngpio = EXYNOS4_GPIO_E3_NR,
2195 .label = "GPE3",
2196 },
2197 }, {
2198 .chip = {
2199 .base = EXYNOS4_GPE4(0),
2200 .ngpio = EXYNOS4_GPIO_E4_NR,
2201 .label = "GPE4",
2202 },
2203 }, {
2204 .chip = {
2205 .base = EXYNOS4_GPF0(0),
2206 .ngpio = EXYNOS4_GPIO_F0_NR,
2207 .label = "GPF0",
2208 },
2209 }, {
2210 .chip = {
2211 .base = EXYNOS4_GPF1(0),
2212 .ngpio = EXYNOS4_GPIO_F1_NR,
2213 .label = "GPF1",
2214 },
2215 }, {
2216 .chip = {
2217 .base = EXYNOS4_GPF2(0),
2218 .ngpio = EXYNOS4_GPIO_F2_NR,
2219 .label = "GPF2",
2220 },
2221 }, {
2222 .chip = {
2223 .base = EXYNOS4_GPF3(0),
2224 .ngpio = EXYNOS4_GPIO_F3_NR,
2225 .label = "GPF3",
2226 },
2227 },
2228};
2229#endif
2230
2231#ifdef CONFIG_ARCH_EXYNOS4
2232static struct samsung_gpio_chip exynos4_gpios_2[] = {
2233 {
2234 .chip = {
2235 .base = EXYNOS4_GPJ0(0),
2236 .ngpio = EXYNOS4_GPIO_J0_NR,
2237 .label = "GPJ0",
2238 },
2239 }, {
2240 .chip = {
2241 .base = EXYNOS4_GPJ1(0),
2242 .ngpio = EXYNOS4_GPIO_J1_NR,
2243 .label = "GPJ1",
2244 },
2245 }, {
2246 .chip = {
2247 .base = EXYNOS4_GPK0(0),
2248 .ngpio = EXYNOS4_GPIO_K0_NR,
2249 .label = "GPK0",
2250 },
2251 }, {
2252 .chip = {
2253 .base = EXYNOS4_GPK1(0),
2254 .ngpio = EXYNOS4_GPIO_K1_NR,
2255 .label = "GPK1",
2256 },
2257 }, {
2258 .chip = {
2259 .base = EXYNOS4_GPK2(0),
2260 .ngpio = EXYNOS4_GPIO_K2_NR,
2261 .label = "GPK2",
2262 },
2263 }, {
2264 .chip = {
2265 .base = EXYNOS4_GPK3(0),
2266 .ngpio = EXYNOS4_GPIO_K3_NR,
2267 .label = "GPK3",
2268 },
2269 }, {
2270 .chip = {
2271 .base = EXYNOS4_GPL0(0),
2272 .ngpio = EXYNOS4_GPIO_L0_NR,
2273 .label = "GPL0",
2274 },
2275 }, {
2276 .chip = {
2277 .base = EXYNOS4_GPL1(0),
2278 .ngpio = EXYNOS4_GPIO_L1_NR,
2279 .label = "GPL1",
2280 },
2281 }, {
2282 .chip = {
2283 .base = EXYNOS4_GPL2(0),
2284 .ngpio = EXYNOS4_GPIO_L2_NR,
2285 .label = "GPL2",
2286 },
2287 }, {
2288 .config = &samsung_gpio_cfgs[8],
2289 .chip = {
2290 .base = EXYNOS4_GPY0(0),
2291 .ngpio = EXYNOS4_GPIO_Y0_NR,
2292 .label = "GPY0",
2293 },
2294 }, {
2295 .config = &samsung_gpio_cfgs[8],
2296 .chip = {
2297 .base = EXYNOS4_GPY1(0),
2298 .ngpio = EXYNOS4_GPIO_Y1_NR,
2299 .label = "GPY1",
2300 },
2301 }, {
2302 .config = &samsung_gpio_cfgs[8],
2303 .chip = {
2304 .base = EXYNOS4_GPY2(0),
2305 .ngpio = EXYNOS4_GPIO_Y2_NR,
2306 .label = "GPY2",
2307 },
2308 }, {
2309 .config = &samsung_gpio_cfgs[8],
2310 .chip = {
2311 .base = EXYNOS4_GPY3(0),
2312 .ngpio = EXYNOS4_GPIO_Y3_NR,
2313 .label = "GPY3",
2314 },
2315 }, {
2316 .config = &samsung_gpio_cfgs[8],
2317 .chip = {
2318 .base = EXYNOS4_GPY4(0),
2319 .ngpio = EXYNOS4_GPIO_Y4_NR,
2320 .label = "GPY4",
2321 },
2322 }, {
2323 .config = &samsung_gpio_cfgs[8],
2324 .chip = {
2325 .base = EXYNOS4_GPY5(0),
2326 .ngpio = EXYNOS4_GPIO_Y5_NR,
2327 .label = "GPY5",
2328 },
2329 }, {
2330 .config = &samsung_gpio_cfgs[8],
2331 .chip = {
2332 .base = EXYNOS4_GPY6(0),
2333 .ngpio = EXYNOS4_GPIO_Y6_NR,
2334 .label = "GPY6",
2335 },
2336 }, {
2337 .config = &samsung_gpio_cfgs[9],
2338 .irq_base = IRQ_EINT(0),
2339 .chip = {
2340 .base = EXYNOS4_GPX0(0),
2341 .ngpio = EXYNOS4_GPIO_X0_NR,
2342 .label = "GPX0",
2343 .to_irq = samsung_gpiolib_to_irq,
2344 },
2345 }, {
2346 .config = &samsung_gpio_cfgs[9],
2347 .irq_base = IRQ_EINT(8),
2348 .chip = {
2349 .base = EXYNOS4_GPX1(0),
2350 .ngpio = EXYNOS4_GPIO_X1_NR,
2351 .label = "GPX1",
2352 .to_irq = samsung_gpiolib_to_irq,
2353 },
2354 }, {
2355 .config = &samsung_gpio_cfgs[9],
2356 .irq_base = IRQ_EINT(16),
2357 .chip = {
2358 .base = EXYNOS4_GPX2(0),
2359 .ngpio = EXYNOS4_GPIO_X2_NR,
2360 .label = "GPX2",
2361 .to_irq = samsung_gpiolib_to_irq,
2362 },
2363 }, {
2364 .config = &samsung_gpio_cfgs[9],
2365 .irq_base = IRQ_EINT(24),
2366 .chip = {
2367 .base = EXYNOS4_GPX3(0),
2368 .ngpio = EXYNOS4_GPIO_X3_NR,
2369 .label = "GPX3",
2370 .to_irq = samsung_gpiolib_to_irq,
2371 },
2372 },
2373};
2374#endif
2375
2376#ifdef CONFIG_ARCH_EXYNOS4
2377static struct samsung_gpio_chip exynos4_gpios_3[] = {
2378 {
2379 .chip = {
2380 .base = EXYNOS4_GPZ(0),
2381 .ngpio = EXYNOS4_GPIO_Z_NR,
2382 .label = "GPZ",
2383 },
2384 },
2385};
2386#endif
2387
2388#ifdef CONFIG_SOC_EXYNOS5250
2389static struct samsung_gpio_chip exynos5_gpios_1[] = {
2390 {
2391 .chip = {
2392 .base = EXYNOS5_GPA0(0),
2393 .ngpio = EXYNOS5_GPIO_A0_NR,
2394 .label = "GPA0",
2395 },
2396 }, {
2397 .chip = {
2398 .base = EXYNOS5_GPA1(0),
2399 .ngpio = EXYNOS5_GPIO_A1_NR,
2400 .label = "GPA1",
2401 },
2402 }, {
2403 .chip = {
2404 .base = EXYNOS5_GPA2(0),
2405 .ngpio = EXYNOS5_GPIO_A2_NR,
2406 .label = "GPA2",
2407 },
2408 }, {
2409 .chip = {
2410 .base = EXYNOS5_GPB0(0),
2411 .ngpio = EXYNOS5_GPIO_B0_NR,
2412 .label = "GPB0",
2413 },
2414 }, {
2415 .chip = {
2416 .base = EXYNOS5_GPB1(0),
2417 .ngpio = EXYNOS5_GPIO_B1_NR,
2418 .label = "GPB1",
2419 },
2420 }, {
2421 .chip = {
2422 .base = EXYNOS5_GPB2(0),
2423 .ngpio = EXYNOS5_GPIO_B2_NR,
2424 .label = "GPB2",
2425 },
2426 }, {
2427 .chip = {
2428 .base = EXYNOS5_GPB3(0),
2429 .ngpio = EXYNOS5_GPIO_B3_NR,
2430 .label = "GPB3",
2431 },
2432 }, {
2433 .chip = {
2434 .base = EXYNOS5_GPC0(0),
2435 .ngpio = EXYNOS5_GPIO_C0_NR,
2436 .label = "GPC0",
2437 },
2438 }, {
2439 .chip = {
2440 .base = EXYNOS5_GPC1(0),
2441 .ngpio = EXYNOS5_GPIO_C1_NR,
2442 .label = "GPC1",
2443 },
2444 }, {
2445 .chip = {
2446 .base = EXYNOS5_GPC2(0),
2447 .ngpio = EXYNOS5_GPIO_C2_NR,
2448 .label = "GPC2",
2449 },
2450 }, {
2451 .chip = {
2452 .base = EXYNOS5_GPC3(0),
2453 .ngpio = EXYNOS5_GPIO_C3_NR,
2454 .label = "GPC3",
2455 },
2456 }, {
2457 .chip = {
2458 .base = EXYNOS5_GPD0(0),
2459 .ngpio = EXYNOS5_GPIO_D0_NR,
2460 .label = "GPD0",
2461 },
2462 }, {
2463 .chip = {
2464 .base = EXYNOS5_GPD1(0),
2465 .ngpio = EXYNOS5_GPIO_D1_NR,
2466 .label = "GPD1",
2467 },
2468 }, {
2469 .chip = {
2470 .base = EXYNOS5_GPY0(0),
2471 .ngpio = EXYNOS5_GPIO_Y0_NR,
2472 .label = "GPY0",
2473 },
2474 }, {
2475 .chip = {
2476 .base = EXYNOS5_GPY1(0),
2477 .ngpio = EXYNOS5_GPIO_Y1_NR,
2478 .label = "GPY1",
2479 },
2480 }, {
2481 .chip = {
2482 .base = EXYNOS5_GPY2(0),
2483 .ngpio = EXYNOS5_GPIO_Y2_NR,
2484 .label = "GPY2",
2485 },
2486 }, {
2487 .chip = {
2488 .base = EXYNOS5_GPY3(0),
2489 .ngpio = EXYNOS5_GPIO_Y3_NR,
2490 .label = "GPY3",
2491 },
2492 }, {
2493 .chip = {
2494 .base = EXYNOS5_GPY4(0),
2495 .ngpio = EXYNOS5_GPIO_Y4_NR,
2496 .label = "GPY4",
2497 },
2498 }, {
2499 .chip = {
2500 .base = EXYNOS5_GPY5(0),
2501 .ngpio = EXYNOS5_GPIO_Y5_NR,
2502 .label = "GPY5",
2503 },
2504 }, {
2505 .chip = {
2506 .base = EXYNOS5_GPY6(0),
2507 .ngpio = EXYNOS5_GPIO_Y6_NR,
2508 .label = "GPY6",
2509 },
2510 }, {
2511 .chip = {
2512 .base = EXYNOS5_GPC4(0),
2513 .ngpio = EXYNOS5_GPIO_C4_NR,
2514 .label = "GPC4",
2515 },
2516 }, {
2517 .config = &samsung_gpio_cfgs[9],
2518 .irq_base = IRQ_EINT(0),
2519 .chip = {
2520 .base = EXYNOS5_GPX0(0),
2521 .ngpio = EXYNOS5_GPIO_X0_NR,
2522 .label = "GPX0",
2523 .to_irq = samsung_gpiolib_to_irq,
2524 },
2525 }, {
2526 .config = &samsung_gpio_cfgs[9],
2527 .irq_base = IRQ_EINT(8),
2528 .chip = {
2529 .base = EXYNOS5_GPX1(0),
2530 .ngpio = EXYNOS5_GPIO_X1_NR,
2531 .label = "GPX1",
2532 .to_irq = samsung_gpiolib_to_irq,
2533 },
2534 }, {
2535 .config = &samsung_gpio_cfgs[9],
2536 .irq_base = IRQ_EINT(16),
2537 .chip = {
2538 .base = EXYNOS5_GPX2(0),
2539 .ngpio = EXYNOS5_GPIO_X2_NR,
2540 .label = "GPX2",
2541 .to_irq = samsung_gpiolib_to_irq,
2542 },
2543 }, {
2544 .config = &samsung_gpio_cfgs[9],
2545 .irq_base = IRQ_EINT(24),
2546 .chip = {
2547 .base = EXYNOS5_GPX3(0),
2548 .ngpio = EXYNOS5_GPIO_X3_NR,
2549 .label = "GPX3",
2550 .to_irq = samsung_gpiolib_to_irq,
2551 },
2552 },
2553};
2554#endif
2555
2556#ifdef CONFIG_SOC_EXYNOS5250
2557static struct samsung_gpio_chip exynos5_gpios_2[] = {
2558 {
2559 .chip = {
2560 .base = EXYNOS5_GPE0(0),
2561 .ngpio = EXYNOS5_GPIO_E0_NR,
2562 .label = "GPE0",
2563 },
2564 }, {
2565 .chip = {
2566 .base = EXYNOS5_GPE1(0),
2567 .ngpio = EXYNOS5_GPIO_E1_NR,
2568 .label = "GPE1",
2569 },
2570 }, {
2571 .chip = {
2572 .base = EXYNOS5_GPF0(0),
2573 .ngpio = EXYNOS5_GPIO_F0_NR,
2574 .label = "GPF0",
2575 },
2576 }, {
2577 .chip = {
2578 .base = EXYNOS5_GPF1(0),
2579 .ngpio = EXYNOS5_GPIO_F1_NR,
2580 .label = "GPF1",
2581 },
2582 }, {
2583 .chip = {
2584 .base = EXYNOS5_GPG0(0),
2585 .ngpio = EXYNOS5_GPIO_G0_NR,
2586 .label = "GPG0",
2587 },
2588 }, {
2589 .chip = {
2590 .base = EXYNOS5_GPG1(0),
2591 .ngpio = EXYNOS5_GPIO_G1_NR,
2592 .label = "GPG1",
2593 },
2594 }, {
2595 .chip = {
2596 .base = EXYNOS5_GPG2(0),
2597 .ngpio = EXYNOS5_GPIO_G2_NR,
2598 .label = "GPG2",
2599 },
2600 }, {
2601 .chip = {
2602 .base = EXYNOS5_GPH0(0),
2603 .ngpio = EXYNOS5_GPIO_H0_NR,
2604 .label = "GPH0",
2605 },
2606 }, {
2607 .chip = {
2608 .base = EXYNOS5_GPH1(0),
2609 .ngpio = EXYNOS5_GPIO_H1_NR,
2610 .label = "GPH1",
2611
2612 },
2613 },
2614};
2615#endif
2616
2617#ifdef CONFIG_SOC_EXYNOS5250
2618static struct samsung_gpio_chip exynos5_gpios_3[] = {
2619 {
2620 .chip = {
2621 .base = EXYNOS5_GPV0(0),
2622 .ngpio = EXYNOS5_GPIO_V0_NR,
2623 .label = "GPV0",
2624 },
2625 }, {
2626 .chip = {
2627 .base = EXYNOS5_GPV1(0),
2628 .ngpio = EXYNOS5_GPIO_V1_NR,
2629 .label = "GPV1",
2630 },
2631 }, {
2632 .chip = {
2633 .base = EXYNOS5_GPV2(0),
2634 .ngpio = EXYNOS5_GPIO_V2_NR,
2635 .label = "GPV2",
2636 },
2637 }, {
2638 .chip = {
2639 .base = EXYNOS5_GPV3(0),
2640 .ngpio = EXYNOS5_GPIO_V3_NR,
2641 .label = "GPV3",
2642 },
2643 }, {
2644 .chip = {
2645 .base = EXYNOS5_GPV4(0),
2646 .ngpio = EXYNOS5_GPIO_V4_NR,
2647 .label = "GPV4",
2648 },
2649 },
2650};
2651#endif
2652
2653#ifdef CONFIG_SOC_EXYNOS5250
2654static struct samsung_gpio_chip exynos5_gpios_4[] = {
2655 {
2656 .chip = {
2657 .base = EXYNOS5_GPZ(0),
2658 .ngpio = EXYNOS5_GPIO_Z_NR,
2659 .label = "GPZ",
2660 },
2661 },
2662};
2663#endif
2664
2665
2666#if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
2667static int exynos_gpio_xlate(struct gpio_chip *gc,
2668 const struct of_phandle_args *gpiospec, u32 *flags)
2669{
2670 unsigned int pin;
2671
2672 if (WARN_ON(gc->of_gpio_n_cells < 4))
2673 return -EINVAL;
2674
2675 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
2676 return -EINVAL;
2677
2678 if (gpiospec->args[0] > gc->ngpio)
2679 return -EINVAL;
2680
2681 pin = gc->base + gpiospec->args[0];
2682
2683 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
2684 pr_warn("gpio_xlate: failed to set pin function\n");
2685 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
2686 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
2687 if (s5p_gpio_set_drvstr(pin, gpiospec->args[3]))
2688 pr_warn("gpio_xlate: failed to set pin drive strength\n");
2689
2690 if (flags)
2691 *flags = gpiospec->args[2] >> 16;
2692
2693 return gpiospec->args[0];
2694}
2695
2696static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
2697 { .compatible = "samsung,exynos4-gpio", },
2698 {}
2699};
2700
2701static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2702 u64 base, u64 offset)
2703{
2704 struct gpio_chip *gc = &chip->chip;
2705 u64 address;
2706
2707 if (!of_have_populated_dt())
2708 return;
2709
2710 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
2711 gc->of_node = of_find_matching_node_by_address(NULL,
2712 exynos_gpio_dt_match, address);
2713 if (!gc->of_node) {
2714 pr_info("gpio: device tree node not found for gpio controller"
2715 " with base address %08llx\n", address);
2716 return;
2717 }
2718 gc->of_gpio_n_cells = 4;
2719 gc->of_xlate = exynos_gpio_xlate;
2720}
2721#elif defined(CONFIG_ARCH_EXYNOS)
2722static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2723 u64 base, u64 offset)
2724{
2725 return;
2726}
2727#endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
2728
2729static __init void exynos4_gpiolib_init(void)
2730{
2731#ifdef CONFIG_CPU_EXYNOS4210
2732 struct samsung_gpio_chip *chip;
2733 int i, nr_chips;
2734 void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
2735 int group = 0;
2736 void __iomem *gpx_base;
2737
2738 /* gpio part1 */
2739 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2740 if (gpio_base1 == NULL) {
2741 pr_err("unable to ioremap for gpio_base1\n");
2742 goto err_ioremap1;
2743 }
2744
2745 chip = exynos4_gpios_1;
2746 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2747
2748 for (i = 0; i < nr_chips; i++, chip++) {
2749 if (!chip->config) {
2750 chip->config = &exynos_gpio_cfg;
2751 chip->group = group++;
2752 }
2753 exynos_gpiolib_attach_ofnode(chip,
2754 EXYNOS4_PA_GPIO1, i * 0x20);
2755 }
2756 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2757 nr_chips, gpio_base1);
2758
2759 /* gpio part2 */
2760 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2761 if (gpio_base2 == NULL) {
2762 pr_err("unable to ioremap for gpio_base2\n");
2763 goto err_ioremap2;
2764 }
2765
2766 /* need to set base address for gpx */
2767 chip = &exynos4_gpios_2[16];
2768 gpx_base = gpio_base2 + 0xC00;
2769 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2770 chip->base = gpx_base;
2771
2772 chip = exynos4_gpios_2;
2773 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2774
2775 for (i = 0; i < nr_chips; i++, chip++) {
2776 if (!chip->config) {
2777 chip->config = &exynos_gpio_cfg;
2778 chip->group = group++;
2779 }
2780 exynos_gpiolib_attach_ofnode(chip,
2781 EXYNOS4_PA_GPIO2, i * 0x20);
2782 }
2783 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2784 nr_chips, gpio_base2);
2785
2786 /* gpio part3 */
2787 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2788 if (gpio_base3 == NULL) {
2789 pr_err("unable to ioremap for gpio_base3\n");
2790 goto err_ioremap3;
2791 }
2792
2793 chip = exynos4_gpios_3;
2794 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2795
2796 for (i = 0; i < nr_chips; i++, chip++) {
2797 if (!chip->config) {
2798 chip->config = &exynos_gpio_cfg;
2799 chip->group = group++;
2800 }
2801 exynos_gpiolib_attach_ofnode(chip,
2802 EXYNOS4_PA_GPIO3, i * 0x20);
2803 }
2804 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2805 nr_chips, gpio_base3);
2806
2807#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2808 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2809 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2810#endif
2811
2812 return;
2813
2814err_ioremap3:
2815 iounmap(gpio_base2);
2816err_ioremap2:
2817 iounmap(gpio_base1);
2818err_ioremap1:
2819 return;
2820#endif /* CONFIG_CPU_EXYNOS4210 */
2821}
2822
2823static __init void exynos5_gpiolib_init(void)
2824{
2825#ifdef CONFIG_SOC_EXYNOS5250
2826 struct samsung_gpio_chip *chip;
2827 int i, nr_chips;
2828 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2829 int group = 0;
2830 void __iomem *gpx_base;
2831
2832 /* gpio part1 */
2833 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2834 if (gpio_base1 == NULL) {
2835 pr_err("unable to ioremap for gpio_base1\n");
2836 goto err_ioremap1;
2837 }
2838
2839 /* need to set base address for gpc4 */
2840 exynos5_gpios_1[20].base = gpio_base1 + 0x2E0;
2841
2842 /* need to set base address for gpx */
2843 chip = &exynos5_gpios_1[21];
2844 gpx_base = gpio_base1 + 0xC00;
2845 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2846 chip->base = gpx_base;
2847
2848 chip = exynos5_gpios_1;
2849 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2850
2851 for (i = 0; i < nr_chips; i++, chip++) {
2852 if (!chip->config) {
2853 chip->config = &exynos_gpio_cfg;
2854 chip->group = group++;
2855 }
2856 exynos_gpiolib_attach_ofnode(chip,
2857 EXYNOS5_PA_GPIO1, i * 0x20);
2858 }
2859 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2860 nr_chips, gpio_base1);
2861
2862 /* gpio part2 */
2863 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2864 if (gpio_base2 == NULL) {
2865 pr_err("unable to ioremap for gpio_base2\n");
2866 goto err_ioremap2;
2867 }
2868
2869 chip = exynos5_gpios_2;
2870 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
2871
2872 for (i = 0; i < nr_chips; i++, chip++) {
2873 if (!chip->config) {
2874 chip->config = &exynos_gpio_cfg;
2875 chip->group = group++;
2876 }
2877 exynos_gpiolib_attach_ofnode(chip,
2878 EXYNOS5_PA_GPIO2, i * 0x20);
2879 }
2880 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
2881 nr_chips, gpio_base2);
2882
2883 /* gpio part3 */
2884 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
2885 if (gpio_base3 == NULL) {
2886 pr_err("unable to ioremap for gpio_base3\n");
2887 goto err_ioremap3;
2888 }
2889
2890 /* need to set base address for gpv */
2891 exynos5_gpios_3[0].base = gpio_base3;
2892 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2893 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2894 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2895 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
2896
2897 chip = exynos5_gpios_3;
2898 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
2899
2900 for (i = 0; i < nr_chips; i++, chip++) {
2901 if (!chip->config) {
2902 chip->config = &exynos_gpio_cfg;
2903 chip->group = group++;
2904 }
2905 exynos_gpiolib_attach_ofnode(chip,
2906 EXYNOS5_PA_GPIO3, i * 0x20);
2907 }
2908 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
2909 nr_chips, gpio_base3);
2910
2911 /* gpio part4 */
2912 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
2913 if (gpio_base4 == NULL) {
2914 pr_err("unable to ioremap for gpio_base4\n");
2915 goto err_ioremap4;
2916 }
2917
2918 chip = exynos5_gpios_4;
2919 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
2920
2921 for (i = 0; i < nr_chips; i++, chip++) {
2922 if (!chip->config) {
2923 chip->config = &exynos_gpio_cfg;
2924 chip->group = group++;
2925 }
2926 exynos_gpiolib_attach_ofnode(chip,
2927 EXYNOS5_PA_GPIO4, i * 0x20);
2928 }
2929 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
2930 nr_chips, gpio_base4);
2931 return;
2932
2933err_ioremap4:
2934 iounmap(gpio_base3);
2935err_ioremap3:
2936 iounmap(gpio_base2);
2937err_ioremap2:
2938 iounmap(gpio_base1);
2939err_ioremap1:
2940 return;
2941
2942#endif /* CONFIG_SOC_EXYNOS5250 */
2943}
2944
2945/* TODO: cleanup soc_is_* */ 2078/* TODO: cleanup soc_is_* */
2946static __init int samsung_gpiolib_init(void) 2079static __init int samsung_gpiolib_init(void)
2947{ 2080{
@@ -3040,10 +2173,6 @@ static __init int samsung_gpiolib_init(void)
3040#if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT) 2173#if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
3041 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); 2174 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3042#endif 2175#endif
3043 } else if (soc_is_exynos4210()) {
3044 exynos4_gpiolib_init();
3045 } else if (soc_is_exynos5250()) {
3046 exynos5_gpiolib_init();
3047 } else { 2176 } else {
3048 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n"); 2177 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
3049 return -ENODEV; 2178 return -ENODEV;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 22:02:27 -0500