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authorArnd Bergmann <arnd@arndb.de>2012-03-15 16:50:16 -0400
committerArnd Bergmann <arnd@arndb.de>2012-03-15 16:50:16 -0400
commit4788d72ce6c0d71220c06a242f935a056eccf424 (patch)
tree851ba5c54b4889b78b2a217c285e87c9e73536d3 /drivers/gpio
parente594a97c8c74533ec105b2ac9194217e918f172f (diff)
parentd39c815278bef7ce896100d8b385c81ed5cac015 (diff)
Merge branch 'next/soc-exynos5250-gpio' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
* 'next/soc-exynos5250-gpio' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (201 commits) gpio/samsung: use ioremap() for EXYNOS4 GPIOlib gpio/samsung: add support GPIOlib for EXYNOS5250 ARM: EXYNOS: add support GPIO for EXYNOS5250 (update to v3.3-rc7) Conflicts: arch/arm/mach-pxa/pxa25x.c arch/arm/mach-pxa/pxa27x.c The dummy clock for the pxa rtc in those files keeps getting added and removed in various trees. Apparently removing is the correct solution. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/gpio-samsung.c487
1 files changed, 445 insertions, 42 deletions
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 0a79a1167a25..46277877b7ec 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -169,7 +169,7 @@ int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
169 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN); 169 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
170} 170}
171 171
172static int exynos4_gpio_setpull(struct samsung_gpio_chip *chip, 172static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
173 unsigned int off, samsung_gpio_pull_t pull) 173 unsigned int off, samsung_gpio_pull_t pull)
174{ 174{
175 if (pull == S3C_GPIO_PULL_UP) 175 if (pull == S3C_GPIO_PULL_UP)
@@ -178,7 +178,7 @@ static int exynos4_gpio_setpull(struct samsung_gpio_chip *chip,
178 return samsung_gpio_setpull_updown(chip, off, pull); 178 return samsung_gpio_setpull_updown(chip, off, pull);
179} 179}
180 180
181static samsung_gpio_pull_t exynos4_gpio_getpull(struct samsung_gpio_chip *chip, 181static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
182 unsigned int off) 182 unsigned int off)
183{ 183{
184 samsung_gpio_pull_t pull; 184 samsung_gpio_pull_t pull;
@@ -452,9 +452,9 @@ static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
452}; 452};
453#endif 453#endif
454 454
455static struct samsung_gpio_cfg exynos4_gpio_cfg = { 455static struct samsung_gpio_cfg exynos_gpio_cfg = {
456 .set_pull = exynos4_gpio_setpull, 456 .set_pull = exynos_gpio_setpull,
457 .get_pull = exynos4_gpio_getpull, 457 .get_pull = exynos_gpio_getpull,
458 .set_config = samsung_gpio_setcfg_4bit, 458 .set_config = samsung_gpio_setcfg_4bit,
459 .get_config = samsung_gpio_getcfg_4bit, 459 .get_config = samsung_gpio_getcfg_4bit,
460}; 460};
@@ -502,13 +502,13 @@ static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
502 .get_config = samsung_gpio_getcfg_2bit, 502 .get_config = samsung_gpio_getcfg_2bit,
503 }, 503 },
504 [8] = { 504 [8] = {
505 .set_pull = exynos4_gpio_setpull, 505 .set_pull = exynos_gpio_setpull,
506 .get_pull = exynos4_gpio_getpull, 506 .get_pull = exynos_gpio_getpull,
507 }, 507 },
508 [9] = { 508 [9] = {
509 .cfg_eint = 0x3, 509 .cfg_eint = 0x3,
510 .set_pull = exynos4_gpio_setpull, 510 .set_pull = exynos_gpio_setpull,
511 .get_pull = exynos4_gpio_getpull, 511 .get_pull = exynos_gpio_getpull,
512 } 512 }
513}; 513};
514 514
@@ -2113,10 +2113,10 @@ static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
2113}; 2113};
2114 2114
2115/* 2115/*
2116 * Followings are the gpio banks in EXYNOS4210 2116 * Followings are the gpio banks in EXYNOS SoCs
2117 * 2117 *
2118 * The 'config' member when left to NULL, is initialized to the default 2118 * The 'config' member when left to NULL, is initialized to the default
2119 * structure samsung_gpio_cfgs[3] in the init function below. 2119 * structure exynos_gpio_cfg in the init function below.
2120 * 2120 *
2121 * The 'base' member is also initialized in the init function below. 2121 * The 'base' member is also initialized in the init function below.
2122 * Note: The initialization of 'base' member of samsung_gpio_chip structure 2122 * Note: The initialization of 'base' member of samsung_gpio_chip structure
@@ -2331,7 +2331,6 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
2331 .label = "GPY6", 2331 .label = "GPY6",
2332 }, 2332 },
2333 }, { 2333 }, {
2334 .base = (S5P_VA_GPIO2 + 0xC00),
2335 .config = &samsung_gpio_cfgs[9], 2334 .config = &samsung_gpio_cfgs[9],
2336 .irq_base = IRQ_EINT(0), 2335 .irq_base = IRQ_EINT(0),
2337 .chip = { 2336 .chip = {
@@ -2341,7 +2340,6 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
2341 .to_irq = samsung_gpiolib_to_irq, 2340 .to_irq = samsung_gpiolib_to_irq,
2342 }, 2341 },
2343 }, { 2342 }, {
2344 .base = (S5P_VA_GPIO2 + 0xC20),
2345 .config = &samsung_gpio_cfgs[9], 2343 .config = &samsung_gpio_cfgs[9],
2346 .irq_base = IRQ_EINT(8), 2344 .irq_base = IRQ_EINT(8),
2347 .chip = { 2345 .chip = {
@@ -2351,7 +2349,6 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
2351 .to_irq = samsung_gpiolib_to_irq, 2349 .to_irq = samsung_gpiolib_to_irq,
2352 }, 2350 },
2353 }, { 2351 }, {
2354 .base = (S5P_VA_GPIO2 + 0xC40),
2355 .config = &samsung_gpio_cfgs[9], 2352 .config = &samsung_gpio_cfgs[9],
2356 .irq_base = IRQ_EINT(16), 2353 .irq_base = IRQ_EINT(16),
2357 .chip = { 2354 .chip = {
@@ -2361,7 +2358,6 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
2361 .to_irq = samsung_gpiolib_to_irq, 2358 .to_irq = samsung_gpiolib_to_irq,
2362 }, 2359 },
2363 }, { 2360 }, {
2364 .base = (S5P_VA_GPIO2 + 0xC60),
2365 .config = &samsung_gpio_cfgs[9], 2361 .config = &samsung_gpio_cfgs[9],
2366 .irq_base = IRQ_EINT(24), 2362 .irq_base = IRQ_EINT(24),
2367 .chip = { 2363 .chip = {
@@ -2386,8 +2382,280 @@ static struct samsung_gpio_chip exynos4_gpios_3[] = {
2386#endif 2382#endif
2387}; 2383};
2388 2384
2389#if defined(CONFIG_ARCH_EXYNOS4) && defined(CONFIG_OF) 2385static struct samsung_gpio_chip exynos5_gpios_1[] = {
2390static int exynos4_gpio_xlate(struct gpio_chip *gc, 2386#ifdef CONFIG_ARCH_EXYNOS5
2387 {
2388 .chip = {
2389 .base = EXYNOS5_GPA0(0),
2390 .ngpio = EXYNOS5_GPIO_A0_NR,
2391 .label = "GPA0",
2392 },
2393 }, {
2394 .chip = {
2395 .base = EXYNOS5_GPA1(0),
2396 .ngpio = EXYNOS5_GPIO_A1_NR,
2397 .label = "GPA1",
2398 },
2399 }, {
2400 .chip = {
2401 .base = EXYNOS5_GPA2(0),
2402 .ngpio = EXYNOS5_GPIO_A2_NR,
2403 .label = "GPA2",
2404 },
2405 }, {
2406 .chip = {
2407 .base = EXYNOS5_GPB0(0),
2408 .ngpio = EXYNOS5_GPIO_B0_NR,
2409 .label = "GPB0",
2410 },
2411 }, {
2412 .chip = {
2413 .base = EXYNOS5_GPB1(0),
2414 .ngpio = EXYNOS5_GPIO_B1_NR,
2415 .label = "GPB1",
2416 },
2417 }, {
2418 .chip = {
2419 .base = EXYNOS5_GPB2(0),
2420 .ngpio = EXYNOS5_GPIO_B2_NR,
2421 .label = "GPB2",
2422 },
2423 }, {
2424 .chip = {
2425 .base = EXYNOS5_GPB3(0),
2426 .ngpio = EXYNOS5_GPIO_B3_NR,
2427 .label = "GPB3",
2428 },
2429 }, {
2430 .chip = {
2431 .base = EXYNOS5_GPC0(0),
2432 .ngpio = EXYNOS5_GPIO_C0_NR,
2433 .label = "GPC0",
2434 },
2435 }, {
2436 .chip = {
2437 .base = EXYNOS5_GPC1(0),
2438 .ngpio = EXYNOS5_GPIO_C1_NR,
2439 .label = "GPC1",
2440 },
2441 }, {
2442 .chip = {
2443 .base = EXYNOS5_GPC2(0),
2444 .ngpio = EXYNOS5_GPIO_C2_NR,
2445 .label = "GPC2",
2446 },
2447 }, {
2448 .chip = {
2449 .base = EXYNOS5_GPC3(0),
2450 .ngpio = EXYNOS5_GPIO_C3_NR,
2451 .label = "GPC3",
2452 },
2453 }, {
2454 .chip = {
2455 .base = EXYNOS5_GPD0(0),
2456 .ngpio = EXYNOS5_GPIO_D0_NR,
2457 .label = "GPD0",
2458 },
2459 }, {
2460 .chip = {
2461 .base = EXYNOS5_GPD1(0),
2462 .ngpio = EXYNOS5_GPIO_D1_NR,
2463 .label = "GPD1",
2464 },
2465 }, {
2466 .chip = {
2467 .base = EXYNOS5_GPY0(0),
2468 .ngpio = EXYNOS5_GPIO_Y0_NR,
2469 .label = "GPY0",
2470 },
2471 }, {
2472 .chip = {
2473 .base = EXYNOS5_GPY1(0),
2474 .ngpio = EXYNOS5_GPIO_Y1_NR,
2475 .label = "GPY1",
2476 },
2477 }, {
2478 .chip = {
2479 .base = EXYNOS5_GPY2(0),
2480 .ngpio = EXYNOS5_GPIO_Y2_NR,
2481 .label = "GPY2",
2482 },
2483 }, {
2484 .chip = {
2485 .base = EXYNOS5_GPY3(0),
2486 .ngpio = EXYNOS5_GPIO_Y3_NR,
2487 .label = "GPY3",
2488 },
2489 }, {
2490 .chip = {
2491 .base = EXYNOS5_GPY4(0),
2492 .ngpio = EXYNOS5_GPIO_Y4_NR,
2493 .label = "GPY4",
2494 },
2495 }, {
2496 .chip = {
2497 .base = EXYNOS5_GPY5(0),
2498 .ngpio = EXYNOS5_GPIO_Y5_NR,
2499 .label = "GPY5",
2500 },
2501 }, {
2502 .chip = {
2503 .base = EXYNOS5_GPY6(0),
2504 .ngpio = EXYNOS5_GPIO_Y6_NR,
2505 .label = "GPY6",
2506 },
2507 }, {
2508 .config = &samsung_gpio_cfgs[9],
2509 .irq_base = IRQ_EINT(0),
2510 .chip = {
2511 .base = EXYNOS5_GPX0(0),
2512 .ngpio = EXYNOS5_GPIO_X0_NR,
2513 .label = "GPX0",
2514 .to_irq = samsung_gpiolib_to_irq,
2515 },
2516 }, {
2517 .config = &samsung_gpio_cfgs[9],
2518 .irq_base = IRQ_EINT(8),
2519 .chip = {
2520 .base = EXYNOS5_GPX1(0),
2521 .ngpio = EXYNOS5_GPIO_X1_NR,
2522 .label = "GPX1",
2523 .to_irq = samsung_gpiolib_to_irq,
2524 },
2525 }, {
2526 .config = &samsung_gpio_cfgs[9],
2527 .irq_base = IRQ_EINT(16),
2528 .chip = {
2529 .base = EXYNOS5_GPX2(0),
2530 .ngpio = EXYNOS5_GPIO_X2_NR,
2531 .label = "GPX2",
2532 .to_irq = samsung_gpiolib_to_irq,
2533 },
2534 }, {
2535 .config = &samsung_gpio_cfgs[9],
2536 .irq_base = IRQ_EINT(24),
2537 .chip = {
2538 .base = EXYNOS5_GPX3(0),
2539 .ngpio = EXYNOS5_GPIO_X3_NR,
2540 .label = "GPX3",
2541 .to_irq = samsung_gpiolib_to_irq,
2542 },
2543 },
2544#endif
2545};
2546
2547static struct samsung_gpio_chip exynos5_gpios_2[] = {
2548#ifdef CONFIG_ARCH_EXYNOS5
2549 {
2550 .chip = {
2551 .base = EXYNOS5_GPE0(0),
2552 .ngpio = EXYNOS5_GPIO_E0_NR,
2553 .label = "GPE0",
2554 },
2555 }, {
2556 .chip = {
2557 .base = EXYNOS5_GPE1(0),
2558 .ngpio = EXYNOS5_GPIO_E1_NR,
2559 .label = "GPE1",
2560 },
2561 }, {
2562 .chip = {
2563 .base = EXYNOS5_GPF0(0),
2564 .ngpio = EXYNOS5_GPIO_F0_NR,
2565 .label = "GPF0",
2566 },
2567 }, {
2568 .chip = {
2569 .base = EXYNOS5_GPF1(0),
2570 .ngpio = EXYNOS5_GPIO_F1_NR,
2571 .label = "GPF1",
2572 },
2573 }, {
2574 .chip = {
2575 .base = EXYNOS5_GPG0(0),
2576 .ngpio = EXYNOS5_GPIO_G0_NR,
2577 .label = "GPG0",
2578 },
2579 }, {
2580 .chip = {
2581 .base = EXYNOS5_GPG1(0),
2582 .ngpio = EXYNOS5_GPIO_G1_NR,
2583 .label = "GPG1",
2584 },
2585 }, {
2586 .chip = {
2587 .base = EXYNOS5_GPG2(0),
2588 .ngpio = EXYNOS5_GPIO_G2_NR,
2589 .label = "GPG2",
2590 },
2591 }, {
2592 .chip = {
2593 .base = EXYNOS5_GPH0(0),
2594 .ngpio = EXYNOS5_GPIO_H0_NR,
2595 .label = "GPH0",
2596 },
2597 }, {
2598 .chip = {
2599 .base = EXYNOS5_GPH1(0),
2600 .ngpio = EXYNOS5_GPIO_H1_NR,
2601 .label = "GPH1",
2602
2603 },
2604 },
2605#endif
2606};
2607
2608static struct samsung_gpio_chip exynos5_gpios_3[] = {
2609#ifdef CONFIG_ARCH_EXYNOS5
2610 {
2611 .chip = {
2612 .base = EXYNOS5_GPV0(0),
2613 .ngpio = EXYNOS5_GPIO_V0_NR,
2614 .label = "GPV0",
2615 },
2616 }, {
2617 .chip = {
2618 .base = EXYNOS5_GPV1(0),
2619 .ngpio = EXYNOS5_GPIO_V1_NR,
2620 .label = "GPV1",
2621 },
2622 }, {
2623 .chip = {
2624 .base = EXYNOS5_GPV2(0),
2625 .ngpio = EXYNOS5_GPIO_V2_NR,
2626 .label = "GPV2",
2627 },
2628 }, {
2629 .chip = {
2630 .base = EXYNOS5_GPV3(0),
2631 .ngpio = EXYNOS5_GPIO_V3_NR,
2632 .label = "GPV3",
2633 },
2634 }, {
2635 .chip = {
2636 .base = EXYNOS5_GPV4(0),
2637 .ngpio = EXYNOS5_GPIO_V4_NR,
2638 .label = "GPV4",
2639 },
2640 },
2641#endif
2642};
2643
2644static struct samsung_gpio_chip exynos5_gpios_4[] = {
2645#ifdef CONFIG_ARCH_EXYNOS5
2646 {
2647 .chip = {
2648 .base = EXYNOS5_GPZ(0),
2649 .ngpio = EXYNOS5_GPIO_Z_NR,
2650 .label = "GPZ",
2651 },
2652 },
2653#endif
2654};
2655
2656
2657#if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
2658static int exynos_gpio_xlate(struct gpio_chip *gc,
2391 const struct of_phandle_args *gpiospec, u32 *flags) 2659 const struct of_phandle_args *gpiospec, u32 *flags)
2392{ 2660{
2393 unsigned int pin; 2661 unsigned int pin;
@@ -2413,13 +2681,13 @@ static int exynos4_gpio_xlate(struct gpio_chip *gc,
2413 return gpiospec->args[0]; 2681 return gpiospec->args[0];
2414} 2682}
2415 2683
2416static const struct of_device_id exynos4_gpio_dt_match[] __initdata = { 2684static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
2417 { .compatible = "samsung,exynos4-gpio", }, 2685 { .compatible = "samsung,exynos4-gpio", },
2418 {} 2686 {}
2419}; 2687};
2420 2688
2421static __init void exynos4_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip, 2689static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2422 u64 base, u64 offset) 2690 u64 base, u64 offset)
2423{ 2691{
2424 struct gpio_chip *gc = &chip->chip; 2692 struct gpio_chip *gc = &chip->chip;
2425 u64 address; 2693 u64 address;
@@ -2429,28 +2697,29 @@ static __init void exynos4_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2429 2697
2430 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset; 2698 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
2431 gc->of_node = of_find_matching_node_by_address(NULL, 2699 gc->of_node = of_find_matching_node_by_address(NULL,
2432 exynos4_gpio_dt_match, address); 2700 exynos_gpio_dt_match, address);
2433 if (!gc->of_node) { 2701 if (!gc->of_node) {
2434 pr_info("gpio: device tree node not found for gpio controller" 2702 pr_info("gpio: device tree node not found for gpio controller"
2435 " with base address %08llx\n", address); 2703 " with base address %08llx\n", address);
2436 return; 2704 return;
2437 } 2705 }
2438 gc->of_gpio_n_cells = 4; 2706 gc->of_gpio_n_cells = 4;
2439 gc->of_xlate = exynos4_gpio_xlate; 2707 gc->of_xlate = exynos_gpio_xlate;
2440} 2708}
2441#elif defined(CONFIG_ARCH_EXYNOS4) 2709#elif defined(CONFIG_ARCH_EXYNOS)
2442static __init void exynos4_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip, 2710static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2443 u64 base, u64 offset) 2711 u64 base, u64 offset)
2444{ 2712{
2445 return; 2713 return;
2446} 2714}
2447#endif /* defined(CONFIG_ARCH_EXYNOS4) && defined(CONFIG_OF) */ 2715#endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
2448 2716
2449/* TODO: cleanup soc_is_* */ 2717/* TODO: cleanup soc_is_* */
2450static __init int samsung_gpiolib_init(void) 2718static __init int samsung_gpiolib_init(void)
2451{ 2719{
2452 struct samsung_gpio_chip *chip; 2720 struct samsung_gpio_chip *chip;
2453 int i, nr_chips; 2721 int i, nr_chips;
2722 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2454 int group = 0; 2723 int group = 0;
2455 2724
2456 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs)); 2725 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
@@ -2516,66 +2785,200 @@ static __init int samsung_gpiolib_init(void)
2516 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); 2785 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2517#endif 2786#endif
2518 } else if (soc_is_exynos4210()) { 2787 } else if (soc_is_exynos4210()) {
2519 group = 0; 2788#ifdef CONFIG_CPU_EXYNOS4210
2789 void __iomem *gpx_base;
2520 2790
2521 /* gpio part1 */ 2791 /* gpio part1 */
2792 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2793 if (gpio_base1 == NULL) {
2794 pr_err("unable to ioremap for gpio_base1\n");
2795 goto err_ioremap1;
2796 }
2797
2522 chip = exynos4_gpios_1; 2798 chip = exynos4_gpios_1;
2523 nr_chips = ARRAY_SIZE(exynos4_gpios_1); 2799 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2524 2800
2525 for (i = 0; i < nr_chips; i++, chip++) { 2801 for (i = 0; i < nr_chips; i++, chip++) {
2526 if (!chip->config) { 2802 if (!chip->config) {
2527 chip->config = &exynos4_gpio_cfg; 2803 chip->config = &exynos_gpio_cfg;
2528 chip->group = group++; 2804 chip->group = group++;
2529 } 2805 }
2530#ifdef CONFIG_CPU_EXYNOS4210 2806 exynos_gpiolib_attach_ofnode(chip,
2531 exynos4_gpiolib_attach_ofnode(chip,
2532 EXYNOS4_PA_GPIO1, i * 0x20); 2807 EXYNOS4_PA_GPIO1, i * 0x20);
2533#endif
2534 } 2808 }
2535 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1, nr_chips, S5P_VA_GPIO1); 2809 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2810 nr_chips, gpio_base1);
2536 2811
2537 /* gpio part2 */ 2812 /* gpio part2 */
2813 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2814 if (gpio_base2 == NULL) {
2815 pr_err("unable to ioremap for gpio_base2\n");
2816 goto err_ioremap2;
2817 }
2818
2819 /* need to set base address for gpx */
2820 chip = &exynos4_gpios_2[16];
2821 gpx_base = gpio_base2 + 0xC00;
2822 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2823 chip->base = gpx_base;
2824
2538 chip = exynos4_gpios_2; 2825 chip = exynos4_gpios_2;
2539 nr_chips = ARRAY_SIZE(exynos4_gpios_2); 2826 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2540 2827
2541 for (i = 0; i < nr_chips; i++, chip++) { 2828 for (i = 0; i < nr_chips; i++, chip++) {
2542 if (!chip->config) { 2829 if (!chip->config) {
2543 chip->config = &exynos4_gpio_cfg; 2830 chip->config = &exynos_gpio_cfg;
2544 chip->group = group++; 2831 chip->group = group++;
2545 } 2832 }
2546#ifdef CONFIG_CPU_EXYNOS4210 2833 exynos_gpiolib_attach_ofnode(chip,
2547 exynos4_gpiolib_attach_ofnode(chip,
2548 EXYNOS4_PA_GPIO2, i * 0x20); 2834 EXYNOS4_PA_GPIO2, i * 0x20);
2549#endif
2550 } 2835 }
2551 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2, nr_chips, S5P_VA_GPIO2); 2836 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2837 nr_chips, gpio_base2);
2552 2838
2553 /* gpio part3 */ 2839 /* gpio part3 */
2840 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2841 if (gpio_base3 == NULL) {
2842 pr_err("unable to ioremap for gpio_base3\n");
2843 goto err_ioremap3;
2844 }
2845
2554 chip = exynos4_gpios_3; 2846 chip = exynos4_gpios_3;
2555 nr_chips = ARRAY_SIZE(exynos4_gpios_3); 2847 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2556 2848
2557 for (i = 0; i < nr_chips; i++, chip++) { 2849 for (i = 0; i < nr_chips; i++, chip++) {
2558 if (!chip->config) { 2850 if (!chip->config) {
2559 chip->config = &exynos4_gpio_cfg; 2851 chip->config = &exynos_gpio_cfg;
2560 chip->group = group++; 2852 chip->group = group++;
2561 } 2853 }
2562#ifdef CONFIG_CPU_EXYNOS4210 2854 exynos_gpiolib_attach_ofnode(chip,
2563 exynos4_gpiolib_attach_ofnode(chip,
2564 EXYNOS4_PA_GPIO3, i * 0x20); 2855 EXYNOS4_PA_GPIO3, i * 0x20);
2565#endif
2566 } 2856 }
2567 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3, nr_chips, S5P_VA_GPIO3); 2857 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2858 nr_chips, gpio_base3);
2568 2859
2569#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT) 2860#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2570 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS); 2861 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2571 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS); 2862 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2572#endif 2863#endif
2864
2865#endif /* CONFIG_CPU_EXYNOS4210 */
2866 } else if (soc_is_exynos5250()) {
2867#ifdef CONFIG_SOC_EXYNOS5250
2868 void __iomem *gpx_base;
2869
2870 /* gpio part1 */
2871 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2872 if (gpio_base1 == NULL) {
2873 pr_err("unable to ioremap for gpio_base1\n");
2874 goto err_ioremap1;
2875 }
2876
2877 /* need to set base address for gpx */
2878 chip = &exynos5_gpios_1[20];
2879 gpx_base = gpio_base1 + 0xC00;
2880 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2881 chip->base = gpx_base;
2882
2883 chip = exynos5_gpios_1;
2884 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2885
2886 for (i = 0; i < nr_chips; i++, chip++) {
2887 if (!chip->config) {
2888 chip->config = &exynos_gpio_cfg;
2889 chip->group = group++;
2890 }
2891 exynos_gpiolib_attach_ofnode(chip,
2892 EXYNOS5_PA_GPIO1, i * 0x20);
2893 }
2894 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2895 nr_chips, gpio_base1);
2896
2897 /* gpio part2 */
2898 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2899 if (gpio_base2 == NULL) {
2900 pr_err("unable to ioremap for gpio_base2\n");
2901 goto err_ioremap2;
2902 }
2903
2904 chip = exynos5_gpios_2;
2905 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
2906
2907 for (i = 0; i < nr_chips; i++, chip++) {
2908 if (!chip->config) {
2909 chip->config = &exynos_gpio_cfg;
2910 chip->group = group++;
2911 }
2912 exynos_gpiolib_attach_ofnode(chip,
2913 EXYNOS5_PA_GPIO2, i * 0x20);
2914 }
2915 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
2916 nr_chips, gpio_base2);
2917
2918 /* gpio part3 */
2919 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
2920 if (gpio_base3 == NULL) {
2921 pr_err("unable to ioremap for gpio_base3\n");
2922 goto err_ioremap3;
2923 }
2924
2925 /* need to set base address for gpv */
2926 exynos5_gpios_3[0].base = gpio_base3;
2927 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2928 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2929 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2930 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
2931
2932 chip = exynos5_gpios_3;
2933 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
2934
2935 for (i = 0; i < nr_chips; i++, chip++) {
2936 if (!chip->config) {
2937 chip->config = &exynos_gpio_cfg;
2938 chip->group = group++;
2939 }
2940 exynos_gpiolib_attach_ofnode(chip,
2941 EXYNOS5_PA_GPIO3, i * 0x20);
2942 }
2943 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
2944 nr_chips, gpio_base3);
2945
2946 /* gpio part4 */
2947 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
2948 if (gpio_base4 == NULL) {
2949 pr_err("unable to ioremap for gpio_base4\n");
2950 goto err_ioremap4;
2951 }
2952
2953 chip = exynos5_gpios_4;
2954 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
2955
2956 for (i = 0; i < nr_chips; i++, chip++) {
2957 if (!chip->config) {
2958 chip->config = &exynos_gpio_cfg;
2959 chip->group = group++;
2960 }
2961 exynos_gpiolib_attach_ofnode(chip,
2962 EXYNOS5_PA_GPIO4, i * 0x20);
2963 }
2964 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
2965 nr_chips, gpio_base4);
2966#endif /* CONFIG_SOC_EXYNOS5250 */
2573 } else { 2967 } else {
2574 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n"); 2968 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
2575 return -ENODEV; 2969 return -ENODEV;
2576 } 2970 }
2577 2971
2578 return 0; 2972 return 0;
2973
2974err_ioremap4:
2975 iounmap(gpio_base3);
2976err_ioremap3:
2977 iounmap(gpio_base2);
2978err_ioremap2:
2979 iounmap(gpio_base1);
2980err_ioremap1:
2981 return -ENOMEM;
2579} 2982}
2580core_initcall(samsung_gpiolib_init); 2983core_initcall(samsung_gpiolib_init);
2581 2984
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 00:43:04 -0500