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authorViresh Kumar <viresh.kumar@st.com>2011-12-13 22:58:27 -0500
committerSamuel Ortiz <sameo@linux.intel.com>2012-01-08 18:37:44 -0500
commitcccdceb938b37a415c42a0635b8a19893a3a19bb (patch)
tree2a6deedeb257a4cd3c39844258c67a1ea30d6b56 /drivers/gpio
parent7f7f4ea15ef4645f3888310a7a761fc2c4f689c9 (diff)
gpio: Add support for stmpe variant 801
STMPE801 is a GPIO expander. GPIO registers for 801 are slightly different from other variants. This patch adds support for STMPE801 in stmpe gpio driver. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@st.com> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/gpio-stmpe.c25
1 files changed, 22 insertions, 3 deletions
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
index 4c980b573328..87a68a896abf 100644
--- a/drivers/gpio/gpio-stmpe.c
+++ b/drivers/gpio/gpio-stmpe.c
@@ -65,7 +65,14 @@ static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
65 u8 reg = stmpe->regs[which] - (offset / 8); 65 u8 reg = stmpe->regs[which] - (offset / 8);
66 u8 mask = 1 << (offset % 8); 66 u8 mask = 1 << (offset % 8);
67 67
68 stmpe_reg_write(stmpe, reg, mask); 68 /*
69 * Some variants have single register for gpio set/clear functionality.
70 * For them we need to write 0 to clear and 1 to set.
71 */
72 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
73 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
74 else
75 stmpe_reg_write(stmpe, reg, mask);
69} 76}
70 77
71static int stmpe_gpio_direction_output(struct gpio_chip *chip, 78static int stmpe_gpio_direction_output(struct gpio_chip *chip,
@@ -132,6 +139,10 @@ static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
132 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) 139 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
133 return -EINVAL; 140 return -EINVAL;
134 141
142 /* STMPE801 doesn't have RE and FE registers */
143 if (stmpe_gpio->stmpe->partnum == STMPE801)
144 return 0;
145
135 if (type == IRQ_TYPE_EDGE_RISING) 146 if (type == IRQ_TYPE_EDGE_RISING)
136 stmpe_gpio->regs[REG_RE][regoffset] |= mask; 147 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
137 else 148 else
@@ -165,6 +176,11 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
165 int i, j; 176 int i, j;
166 177
167 for (i = 0; i < CACHE_NR_REGS; i++) { 178 for (i = 0; i < CACHE_NR_REGS; i++) {
179 /* STMPE801 doesn't have RE and FE registers */
180 if ((stmpe->partnum == STMPE801) &&
181 (i != REG_IE))
182 continue;
183
168 for (j = 0; j < num_banks; j++) { 184 for (j = 0; j < num_banks; j++) {
169 u8 old = stmpe_gpio->oldregs[i][j]; 185 u8 old = stmpe_gpio->oldregs[i][j];
170 u8 new = stmpe_gpio->regs[i][j]; 186 u8 new = stmpe_gpio->regs[i][j];
@@ -241,8 +257,11 @@ static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
241 } 257 }
242 258
243 stmpe_reg_write(stmpe, statmsbreg + i, status[i]); 259 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
244 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] + i, 260
245 status[i]); 261 /* Edge detect register is not present on 801 */
262 if (stmpe->partnum != STMPE801)
263 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
264 + i, status[i]);
246 } 265 }
247 266
248 return IRQ_HANDLED; 267 return IRQ_HANDLED;