aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpio/gpio-samsung.c
diff options
context:
space:
mode:
authorKukjin Kim <kgene.kim@samsung.com>2014-07-01 18:52:17 -0400
committerKukjin Kim <kgene.kim@samsung.com>2014-07-12 18:35:12 -0400
commit0d551c3f0c0f23b9fe754b84d163d29b6b70f04c (patch)
treef79c0c5d0f133f7c7e2eb5945a3d3d63626acf6d /drivers/gpio/gpio-samsung.c
parentb8529ec1c1b0984d2baeda450c28eeb40efc87fe (diff)
gpio: samsung: remov s5pc100 related gpio codes
This patch removes gpio codes for s5pc100 SoC. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'drivers/gpio/gpio-samsung.c')
-rw-r--r--drivers/gpio/gpio-samsung.c276
1 files changed, 0 insertions, 276 deletions
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index d12945cda0b4..7d4281e0d901 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -1170,267 +1170,6 @@ static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1170}; 1170};
1171 1171
1172/* 1172/*
1173 * S5PC100 GPIO bank summary:
1174 *
1175 * Bank GPIOs Style INT Type
1176 * A0 8 4Bit GPIO_INT0
1177 * A1 5 4Bit GPIO_INT1
1178 * B 8 4Bit GPIO_INT2
1179 * C 5 4Bit GPIO_INT3
1180 * D 7 4Bit GPIO_INT4
1181 * E0 8 4Bit GPIO_INT5
1182 * E1 6 4Bit GPIO_INT6
1183 * F0 8 4Bit GPIO_INT7
1184 * F1 8 4Bit GPIO_INT8
1185 * F2 8 4Bit GPIO_INT9
1186 * F3 4 4Bit GPIO_INT10
1187 * G0 8 4Bit GPIO_INT11
1188 * G1 3 4Bit GPIO_INT12
1189 * G2 7 4Bit GPIO_INT13
1190 * G3 7 4Bit GPIO_INT14
1191 * H0 8 4Bit WKUP_INT
1192 * H1 8 4Bit WKUP_INT
1193 * H2 8 4Bit WKUP_INT
1194 * H3 8 4Bit WKUP_INT
1195 * I 8 4Bit GPIO_INT15
1196 * J0 8 4Bit GPIO_INT16
1197 * J1 5 4Bit GPIO_INT17
1198 * J2 8 4Bit GPIO_INT18
1199 * J3 8 4Bit GPIO_INT19
1200 * J4 4 4Bit GPIO_INT20
1201 * K0 8 4Bit None
1202 * K1 6 4Bit None
1203 * K2 8 4Bit None
1204 * K3 8 4Bit None
1205 * L0 8 4Bit None
1206 * L1 8 4Bit None
1207 * L2 8 4Bit None
1208 * L3 8 4Bit None
1209 */
1210
1211static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1212#ifdef CONFIG_CPU_S5PC100
1213 {
1214 .chip = {
1215 .base = S5PC100_GPA0(0),
1216 .ngpio = S5PC100_GPIO_A0_NR,
1217 .label = "GPA0",
1218 },
1219 }, {
1220 .chip = {
1221 .base = S5PC100_GPA1(0),
1222 .ngpio = S5PC100_GPIO_A1_NR,
1223 .label = "GPA1",
1224 },
1225 }, {
1226 .chip = {
1227 .base = S5PC100_GPB(0),
1228 .ngpio = S5PC100_GPIO_B_NR,
1229 .label = "GPB",
1230 },
1231 }, {
1232 .chip = {
1233 .base = S5PC100_GPC(0),
1234 .ngpio = S5PC100_GPIO_C_NR,
1235 .label = "GPC",
1236 },
1237 }, {
1238 .chip = {
1239 .base = S5PC100_GPD(0),
1240 .ngpio = S5PC100_GPIO_D_NR,
1241 .label = "GPD",
1242 },
1243 }, {
1244 .chip = {
1245 .base = S5PC100_GPE0(0),
1246 .ngpio = S5PC100_GPIO_E0_NR,
1247 .label = "GPE0",
1248 },
1249 }, {
1250 .chip = {
1251 .base = S5PC100_GPE1(0),
1252 .ngpio = S5PC100_GPIO_E1_NR,
1253 .label = "GPE1",
1254 },
1255 }, {
1256 .chip = {
1257 .base = S5PC100_GPF0(0),
1258 .ngpio = S5PC100_GPIO_F0_NR,
1259 .label = "GPF0",
1260 },
1261 }, {
1262 .chip = {
1263 .base = S5PC100_GPF1(0),
1264 .ngpio = S5PC100_GPIO_F1_NR,
1265 .label = "GPF1",
1266 },
1267 }, {
1268 .chip = {
1269 .base = S5PC100_GPF2(0),
1270 .ngpio = S5PC100_GPIO_F2_NR,
1271 .label = "GPF2",
1272 },
1273 }, {
1274 .chip = {
1275 .base = S5PC100_GPF3(0),
1276 .ngpio = S5PC100_GPIO_F3_NR,
1277 .label = "GPF3",
1278 },
1279 }, {
1280 .chip = {
1281 .base = S5PC100_GPG0(0),
1282 .ngpio = S5PC100_GPIO_G0_NR,
1283 .label = "GPG0",
1284 },
1285 }, {
1286 .chip = {
1287 .base = S5PC100_GPG1(0),
1288 .ngpio = S5PC100_GPIO_G1_NR,
1289 .label = "GPG1",
1290 },
1291 }, {
1292 .chip = {
1293 .base = S5PC100_GPG2(0),
1294 .ngpio = S5PC100_GPIO_G2_NR,
1295 .label = "GPG2",
1296 },
1297 }, {
1298 .chip = {
1299 .base = S5PC100_GPG3(0),
1300 .ngpio = S5PC100_GPIO_G3_NR,
1301 .label = "GPG3",
1302 },
1303 }, {
1304 .chip = {
1305 .base = S5PC100_GPI(0),
1306 .ngpio = S5PC100_GPIO_I_NR,
1307 .label = "GPI",
1308 },
1309 }, {
1310 .chip = {
1311 .base = S5PC100_GPJ0(0),
1312 .ngpio = S5PC100_GPIO_J0_NR,
1313 .label = "GPJ0",
1314 },
1315 }, {
1316 .chip = {
1317 .base = S5PC100_GPJ1(0),
1318 .ngpio = S5PC100_GPIO_J1_NR,
1319 .label = "GPJ1",
1320 },
1321 }, {
1322 .chip = {
1323 .base = S5PC100_GPJ2(0),
1324 .ngpio = S5PC100_GPIO_J2_NR,
1325 .label = "GPJ2",
1326 },
1327 }, {
1328 .chip = {
1329 .base = S5PC100_GPJ3(0),
1330 .ngpio = S5PC100_GPIO_J3_NR,
1331 .label = "GPJ3",
1332 },
1333 }, {
1334 .chip = {
1335 .base = S5PC100_GPJ4(0),
1336 .ngpio = S5PC100_GPIO_J4_NR,
1337 .label = "GPJ4",
1338 },
1339 }, {
1340 .chip = {
1341 .base = S5PC100_GPK0(0),
1342 .ngpio = S5PC100_GPIO_K0_NR,
1343 .label = "GPK0",
1344 },
1345 }, {
1346 .chip = {
1347 .base = S5PC100_GPK1(0),
1348 .ngpio = S5PC100_GPIO_K1_NR,
1349 .label = "GPK1",
1350 },
1351 }, {
1352 .chip = {
1353 .base = S5PC100_GPK2(0),
1354 .ngpio = S5PC100_GPIO_K2_NR,
1355 .label = "GPK2",
1356 },
1357 }, {
1358 .chip = {
1359 .base = S5PC100_GPK3(0),
1360 .ngpio = S5PC100_GPIO_K3_NR,
1361 .label = "GPK3",
1362 },
1363 }, {
1364 .chip = {
1365 .base = S5PC100_GPL0(0),
1366 .ngpio = S5PC100_GPIO_L0_NR,
1367 .label = "GPL0",
1368 },
1369 }, {
1370 .chip = {
1371 .base = S5PC100_GPL1(0),
1372 .ngpio = S5PC100_GPIO_L1_NR,
1373 .label = "GPL1",
1374 },
1375 }, {
1376 .chip = {
1377 .base = S5PC100_GPL2(0),
1378 .ngpio = S5PC100_GPIO_L2_NR,
1379 .label = "GPL2",
1380 },
1381 }, {
1382 .chip = {
1383 .base = S5PC100_GPL3(0),
1384 .ngpio = S5PC100_GPIO_L3_NR,
1385 .label = "GPL3",
1386 },
1387 }, {
1388 .chip = {
1389 .base = S5PC100_GPL4(0),
1390 .ngpio = S5PC100_GPIO_L4_NR,
1391 .label = "GPL4",
1392 },
1393 }, {
1394 .base = (S5P_VA_GPIO + 0xC00),
1395 .irq_base = IRQ_EINT(0),
1396 .chip = {
1397 .base = S5PC100_GPH0(0),
1398 .ngpio = S5PC100_GPIO_H0_NR,
1399 .label = "GPH0",
1400 .to_irq = samsung_gpiolib_to_irq,
1401 },
1402 }, {
1403 .base = (S5P_VA_GPIO + 0xC20),
1404 .irq_base = IRQ_EINT(8),
1405 .chip = {
1406 .base = S5PC100_GPH1(0),
1407 .ngpio = S5PC100_GPIO_H1_NR,
1408 .label = "GPH1",
1409 .to_irq = samsung_gpiolib_to_irq,
1410 },
1411 }, {
1412 .base = (S5P_VA_GPIO + 0xC40),
1413 .irq_base = IRQ_EINT(16),
1414 .chip = {
1415 .base = S5PC100_GPH2(0),
1416 .ngpio = S5PC100_GPIO_H2_NR,
1417 .label = "GPH2",
1418 .to_irq = samsung_gpiolib_to_irq,
1419 },
1420 }, {
1421 .base = (S5P_VA_GPIO + 0xC60),
1422 .irq_base = IRQ_EINT(24),
1423 .chip = {
1424 .base = S5PC100_GPH3(0),
1425 .ngpio = S5PC100_GPIO_H3_NR,
1426 .label = "GPH3",
1427 .to_irq = samsung_gpiolib_to_irq,
1428 },
1429 },
1430#endif
1431};
1432
1433/*
1434 * Followings are the gpio banks in S5PV210/S5PC110 1173 * Followings are the gpio banks in S5PV210/S5PC110
1435 * 1174 *
1436 * The 'config' member when left to NULL, is initialized to the default 1175 * The 'config' member when left to NULL, is initialized to the default
@@ -1681,21 +1420,6 @@ static __init int samsung_gpiolib_init(void)
1681 S3C64XX_VA_GPIO); 1420 S3C64XX_VA_GPIO);
1682 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2, 1421 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
1683 ARRAY_SIZE(s3c64xx_gpios_4bit2)); 1422 ARRAY_SIZE(s3c64xx_gpios_4bit2));
1684 } else if (soc_is_s5pc100()) {
1685 group = 0;
1686 chip = s5pc100_gpios_4bit;
1687 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
1688
1689 for (i = 0; i < nr_chips; i++, chip++) {
1690 if (!chip->config) {
1691 chip->config = &samsung_gpio_cfgs[3];
1692 chip->group = group++;
1693 }
1694 }
1695 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
1696#if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
1697 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
1698#endif
1699 } else if (soc_is_s5pv210()) { 1423 } else if (soc_is_s5pv210()) {
1700 group = 0; 1424 group = 0;
1701 chip = s5pv210_gpios_4bit; 1425 chip = s5pv210_gpios_4bit;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 15:42:05 -0500