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authorGregory CLEMENT <gregory.clement@free-electrons.com>2013-01-22 16:10:23 -0500
committerLinus Walleij <linus.walleij@linaro.org>2013-01-25 03:02:10 -0500
commitf5f0b7aa897ebf6b0d077356a787526212460dd7 (patch)
treefb3eaa1341c6e1f61cfb2cb437c1706c22b66471 /drivers/gpio/gpio-pca953x.c
parent5985d76cc1b62125301754c9b636a18c346bfc52 (diff)
gpio: pca953x: make the register access by GPIO bank
Until now the pca953x driver accessed all the bank of a given register in a single command using only a 32 bits variable. New expanders from the pca53x family come with 40 GPIOs which no more fit in a 32 variable. This patch make access to the registers more generic by relying on an array of u8 variables. This fits exactly the way the registers are represented in the hardware. It also adds helpers to access to a single register of a bank instead of reading or writing all the banks for a given register. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/gpio/gpio-pca953x.c')
-rw-r--r--drivers/gpio/gpio-pca953x.c281
1 files changed, 175 insertions, 106 deletions
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index cc102d25ee24..b35ba0690163 100644
--- a/drivers/gpio/gpio-pca953x.c
+++ b/drivers/gpio/gpio-pca953x.c
@@ -71,18 +71,23 @@ static const struct i2c_device_id pca953x_id[] = {
71}; 71};
72MODULE_DEVICE_TABLE(i2c, pca953x_id); 72MODULE_DEVICE_TABLE(i2c, pca953x_id);
73 73
74#define MAX_BANK 5
75#define BANK_SZ 8
76
77#define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
78
74struct pca953x_chip { 79struct pca953x_chip {
75 unsigned gpio_start; 80 unsigned gpio_start;
76 u32 reg_output; 81 u8 reg_output[MAX_BANK];
77 u32 reg_direction; 82 u8 reg_direction[MAX_BANK];
78 struct mutex i2c_lock; 83 struct mutex i2c_lock;
79 84
80#ifdef CONFIG_GPIO_PCA953X_IRQ 85#ifdef CONFIG_GPIO_PCA953X_IRQ
81 struct mutex irq_lock; 86 struct mutex irq_lock;
82 u32 irq_mask; 87 u8 irq_mask[MAX_BANK];
83 u32 irq_stat; 88 u8 irq_stat[MAX_BANK];
84 u32 irq_trig_raise; 89 u8 irq_trig_raise[MAX_BANK];
85 u32 irq_trig_fall; 90 u8 irq_trig_fall[MAX_BANK];
86 int irq_base; 91 int irq_base;
87 struct irq_domain *domain; 92 struct irq_domain *domain;
88#endif 93#endif
@@ -93,33 +98,69 @@ struct pca953x_chip {
93 int chip_type; 98 int chip_type;
94}; 99};
95 100
96static int pca953x_write_reg(struct pca953x_chip *chip, int reg, u32 val) 101static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
102 int off)
103{
104 int ret;
105 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
106 int offset = off / BANK_SZ;
107
108 ret = i2c_smbus_read_byte_data(chip->client,
109 (reg << bank_shift) + offset);
110 *val = ret;
111
112 if (ret < 0) {
113 dev_err(&chip->client->dev, "failed reading register\n");
114 return ret;
115 }
116
117 return 0;
118}
119
120static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
121 int off)
122{
123 int ret = 0;
124 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
125 int offset = off / BANK_SZ;
126
127 ret = i2c_smbus_write_byte_data(chip->client,
128 (reg << bank_shift) + offset, val);
129
130 if (ret < 0) {
131 dev_err(&chip->client->dev, "failed writing register\n");
132 return ret;
133 }
134
135 return 0;
136}
137
138static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
97{ 139{
98 int ret = 0; 140 int ret = 0;
99 141
100 if (chip->gpio_chip.ngpio <= 8) 142 if (chip->gpio_chip.ngpio <= 8)
101 ret = i2c_smbus_write_byte_data(chip->client, reg, val); 143 ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
102 else if (chip->gpio_chip.ngpio == 24) { 144 else if (chip->gpio_chip.ngpio >= 24) {
103 cpu_to_le32s(&val); 145 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
104 ret = i2c_smbus_write_i2c_block_data(chip->client, 146 ret = i2c_smbus_write_i2c_block_data(chip->client,
105 (reg << 2) | REG_ADDR_AI, 147 (reg << bank_shift) | REG_ADDR_AI,
106 3, 148 NBANK(chip), val);
107 (u8 *) &val);
108 } 149 }
109 else { 150 else {
110 switch (chip->chip_type) { 151 switch (chip->chip_type) {
111 case PCA953X_TYPE: 152 case PCA953X_TYPE:
112 ret = i2c_smbus_write_word_data(chip->client, 153 ret = i2c_smbus_write_word_data(chip->client,
113 reg << 1, val); 154 reg << 1, (u16) *val);
114 break; 155 break;
115 case PCA957X_TYPE: 156 case PCA957X_TYPE:
116 ret = i2c_smbus_write_byte_data(chip->client, reg << 1, 157 ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
117 val & 0xff); 158 val[0]);
118 if (ret < 0) 159 if (ret < 0)
119 break; 160 break;
120 ret = i2c_smbus_write_byte_data(chip->client, 161 ret = i2c_smbus_write_byte_data(chip->client,
121 (reg << 1) + 1, 162 (reg << 1) + 1,
122 (val & 0xff00) >> 8); 163 val[1]);
123 break; 164 break;
124 } 165 }
125 } 166 }
@@ -132,26 +173,24 @@ static int pca953x_write_reg(struct pca953x_chip *chip, int reg, u32 val)
132 return 0; 173 return 0;
133} 174}
134 175
135static int pca953x_read_reg(struct pca953x_chip *chip, int reg, u32 *val) 176static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
136{ 177{
137 int ret; 178 int ret;
138 179
139 if (chip->gpio_chip.ngpio <= 8) { 180 if (chip->gpio_chip.ngpio <= 8) {
140 ret = i2c_smbus_read_byte_data(chip->client, reg); 181 ret = i2c_smbus_read_byte_data(chip->client, reg);
141 *val = ret; 182 *val = ret;
142 } 183 } else if (chip->gpio_chip.ngpio >= 24) {
143 else if (chip->gpio_chip.ngpio == 24) { 184 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
144 *val = 0; 185
145 ret = i2c_smbus_read_i2c_block_data(chip->client, 186 ret = i2c_smbus_read_i2c_block_data(chip->client,
146 (reg << 2) | REG_ADDR_AI, 187 (reg << bank_shift) | REG_ADDR_AI,
147 3, 188 NBANK(chip), val);
148 (u8 *) val);
149 le32_to_cpus(val);
150 } else { 189 } else {
151 ret = i2c_smbus_read_word_data(chip->client, reg << 1); 190 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
152 *val = ret; 191 val[0] = (u16)ret & 0xFF;
192 val[1] = (u16)ret >> 8;
153 } 193 }
154
155 if (ret < 0) { 194 if (ret < 0) {
156 dev_err(&chip->client->dev, "failed reading register\n"); 195 dev_err(&chip->client->dev, "failed reading register\n");
157 return ret; 196 return ret;
@@ -163,13 +202,13 @@ static int pca953x_read_reg(struct pca953x_chip *chip, int reg, u32 *val)
163static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) 202static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
164{ 203{
165 struct pca953x_chip *chip; 204 struct pca953x_chip *chip;
166 uint reg_val; 205 u8 reg_val;
167 int ret, offset = 0; 206 int ret, offset = 0;
168 207
169 chip = container_of(gc, struct pca953x_chip, gpio_chip); 208 chip = container_of(gc, struct pca953x_chip, gpio_chip);
170 209
171 mutex_lock(&chip->i2c_lock); 210 mutex_lock(&chip->i2c_lock);
172 reg_val = chip->reg_direction | (1u << off); 211 reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
173 212
174 switch (chip->chip_type) { 213 switch (chip->chip_type) {
175 case PCA953X_TYPE: 214 case PCA953X_TYPE:
@@ -179,11 +218,11 @@ static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
179 offset = PCA957X_CFG; 218 offset = PCA957X_CFG;
180 break; 219 break;
181 } 220 }
182 ret = pca953x_write_reg(chip, offset, reg_val); 221 ret = pca953x_write_single(chip, offset, reg_val, off);
183 if (ret) 222 if (ret)
184 goto exit; 223 goto exit;
185 224
186 chip->reg_direction = reg_val; 225 chip->reg_direction[off / BANK_SZ] = reg_val;
187 ret = 0; 226 ret = 0;
188exit: 227exit:
189 mutex_unlock(&chip->i2c_lock); 228 mutex_unlock(&chip->i2c_lock);
@@ -194,7 +233,7 @@ static int pca953x_gpio_direction_output(struct gpio_chip *gc,
194 unsigned off, int val) 233 unsigned off, int val)
195{ 234{
196 struct pca953x_chip *chip; 235 struct pca953x_chip *chip;
197 uint reg_val; 236 u8 reg_val;
198 int ret, offset = 0; 237 int ret, offset = 0;
199 238
200 chip = container_of(gc, struct pca953x_chip, gpio_chip); 239 chip = container_of(gc, struct pca953x_chip, gpio_chip);
@@ -202,9 +241,11 @@ static int pca953x_gpio_direction_output(struct gpio_chip *gc,
202 mutex_lock(&chip->i2c_lock); 241 mutex_lock(&chip->i2c_lock);
203 /* set output level */ 242 /* set output level */
204 if (val) 243 if (val)
205 reg_val = chip->reg_output | (1u << off); 244 reg_val = chip->reg_output[off / BANK_SZ]
245 | (1u << (off % BANK_SZ));
206 else 246 else
207 reg_val = chip->reg_output & ~(1u << off); 247 reg_val = chip->reg_output[off / BANK_SZ]
248 & ~(1u << (off % BANK_SZ));
208 249
209 switch (chip->chip_type) { 250 switch (chip->chip_type) {
210 case PCA953X_TYPE: 251 case PCA953X_TYPE:
@@ -214,14 +255,14 @@ static int pca953x_gpio_direction_output(struct gpio_chip *gc,
214 offset = PCA957X_OUT; 255 offset = PCA957X_OUT;
215 break; 256 break;
216 } 257 }
217 ret = pca953x_write_reg(chip, offset, reg_val); 258 ret = pca953x_write_single(chip, offset, reg_val, off);
218 if (ret) 259 if (ret)
219 goto exit; 260 goto exit;
220 261
221 chip->reg_output = reg_val; 262 chip->reg_output[off / BANK_SZ] = reg_val;
222 263
223 /* then direction */ 264 /* then direction */
224 reg_val = chip->reg_direction & ~(1u << off); 265 reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
225 switch (chip->chip_type) { 266 switch (chip->chip_type) {
226 case PCA953X_TYPE: 267 case PCA953X_TYPE:
227 offset = PCA953X_DIRECTION; 268 offset = PCA953X_DIRECTION;
@@ -230,11 +271,11 @@ static int pca953x_gpio_direction_output(struct gpio_chip *gc,
230 offset = PCA957X_CFG; 271 offset = PCA957X_CFG;
231 break; 272 break;
232 } 273 }
233 ret = pca953x_write_reg(chip, offset, reg_val); 274 ret = pca953x_write_single(chip, offset, reg_val, off);
234 if (ret) 275 if (ret)
235 goto exit; 276 goto exit;
236 277
237 chip->reg_direction = reg_val; 278 chip->reg_direction[off / BANK_SZ] = reg_val;
238 ret = 0; 279 ret = 0;
239exit: 280exit:
240 mutex_unlock(&chip->i2c_lock); 281 mutex_unlock(&chip->i2c_lock);
@@ -258,7 +299,7 @@ static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
258 offset = PCA957X_IN; 299 offset = PCA957X_IN;
259 break; 300 break;
260 } 301 }
261 ret = pca953x_read_reg(chip, offset, &reg_val); 302 ret = pca953x_read_single(chip, offset, &reg_val, off);
262 mutex_unlock(&chip->i2c_lock); 303 mutex_unlock(&chip->i2c_lock);
263 if (ret < 0) { 304 if (ret < 0) {
264 /* NOTE: diagnostic already emitted; that's all we should 305 /* NOTE: diagnostic already emitted; that's all we should
@@ -274,16 +315,18 @@ static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
274static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) 315static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
275{ 316{
276 struct pca953x_chip *chip; 317 struct pca953x_chip *chip;
277 u32 reg_val; 318 u8 reg_val;
278 int ret, offset = 0; 319 int ret, offset = 0;
279 320
280 chip = container_of(gc, struct pca953x_chip, gpio_chip); 321 chip = container_of(gc, struct pca953x_chip, gpio_chip);
281 322
282 mutex_lock(&chip->i2c_lock); 323 mutex_lock(&chip->i2c_lock);
283 if (val) 324 if (val)
284 reg_val = chip->reg_output | (1u << off); 325 reg_val = chip->reg_output[off / BANK_SZ]
326 | (1u << (off % BANK_SZ));
285 else 327 else
286 reg_val = chip->reg_output & ~(1u << off); 328 reg_val = chip->reg_output[off / BANK_SZ]
329 & ~(1u << (off % BANK_SZ));
287 330
288 switch (chip->chip_type) { 331 switch (chip->chip_type) {
289 case PCA953X_TYPE: 332 case PCA953X_TYPE:
@@ -293,11 +336,11 @@ static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
293 offset = PCA957X_OUT; 336 offset = PCA957X_OUT;
294 break; 337 break;
295 } 338 }
296 ret = pca953x_write_reg(chip, offset, reg_val); 339 ret = pca953x_write_single(chip, offset, reg_val, off);
297 if (ret) 340 if (ret)
298 goto exit; 341 goto exit;
299 342
300 chip->reg_output = reg_val; 343 chip->reg_output[off / BANK_SZ] = reg_val;
301exit: 344exit:
302 mutex_unlock(&chip->i2c_lock); 345 mutex_unlock(&chip->i2c_lock);
303} 346}
@@ -335,14 +378,14 @@ static void pca953x_irq_mask(struct irq_data *d)
335{ 378{
336 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); 379 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
337 380
338 chip->irq_mask &= ~(1 << d->hwirq); 381 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
339} 382}
340 383
341static void pca953x_irq_unmask(struct irq_data *d) 384static void pca953x_irq_unmask(struct irq_data *d)
342{ 385{
343 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); 386 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
344 387
345 chip->irq_mask |= 1 << d->hwirq; 388 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
346} 389}
347 390
348static void pca953x_irq_bus_lock(struct irq_data *d) 391static void pca953x_irq_bus_lock(struct irq_data *d)
@@ -355,17 +398,20 @@ static void pca953x_irq_bus_lock(struct irq_data *d)
355static void pca953x_irq_bus_sync_unlock(struct irq_data *d) 398static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
356{ 399{
357 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); 400 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
358 u32 new_irqs; 401 u8 new_irqs;
359 u32 level; 402 int level, i;
360 403
361 /* Look for any newly setup interrupt */ 404 /* Look for any newly setup interrupt */
362 new_irqs = chip->irq_trig_fall | chip->irq_trig_raise; 405 for (i = 0; i < NBANK(chip); i++) {
363 new_irqs &= ~chip->reg_direction; 406 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
364 407 new_irqs &= ~chip->reg_direction[i];
365 while (new_irqs) { 408
366 level = __ffs(new_irqs); 409 while (new_irqs) {
367 pca953x_gpio_direction_input(&chip->gpio_chip, level); 410 level = __ffs(new_irqs);
368 new_irqs &= ~(1 << level); 411 pca953x_gpio_direction_input(&chip->gpio_chip,
412 level + (BANK_SZ * i));
413 new_irqs &= ~(1 << level);
414 }
369 } 415 }
370 416
371 mutex_unlock(&chip->irq_lock); 417 mutex_unlock(&chip->irq_lock);
@@ -374,7 +420,8 @@ static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
374static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) 420static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
375{ 421{
376 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d); 422 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
377 u32 mask = 1 << d->hwirq; 423 int bank_nb = d->hwirq / BANK_SZ;
424 u8 mask = 1 << (d->hwirq % BANK_SZ);
378 425
379 if (!(type & IRQ_TYPE_EDGE_BOTH)) { 426 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
380 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", 427 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
@@ -383,14 +430,14 @@ static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
383 } 430 }
384 431
385 if (type & IRQ_TYPE_EDGE_FALLING) 432 if (type & IRQ_TYPE_EDGE_FALLING)
386 chip->irq_trig_fall |= mask; 433 chip->irq_trig_fall[bank_nb] |= mask;
387 else 434 else
388 chip->irq_trig_fall &= ~mask; 435 chip->irq_trig_fall[bank_nb] &= ~mask;
389 436
390 if (type & IRQ_TYPE_EDGE_RISING) 437 if (type & IRQ_TYPE_EDGE_RISING)
391 chip->irq_trig_raise |= mask; 438 chip->irq_trig_raise[bank_nb] |= mask;
392 else 439 else
393 chip->irq_trig_raise &= ~mask; 440 chip->irq_trig_raise[bank_nb] &= ~mask;
394 441
395 return 0; 442 return 0;
396} 443}
@@ -404,13 +451,13 @@ static struct irq_chip pca953x_irq_chip = {
404 .irq_set_type = pca953x_irq_set_type, 451 .irq_set_type = pca953x_irq_set_type,
405}; 452};
406 453
407static u32 pca953x_irq_pending(struct pca953x_chip *chip) 454static u8 pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
408{ 455{
409 u32 cur_stat; 456 u8 cur_stat[MAX_BANK];
410 u32 old_stat; 457 u8 old_stat[MAX_BANK];
411 u32 pending; 458 u8 pendings = 0;
412 u32 trigger; 459 u8 trigger[MAX_BANK], triggers = 0;
413 int ret, offset = 0; 460 int ret, i, offset = 0;
414 461
415 switch (chip->chip_type) { 462 switch (chip->chip_type) {
416 case PCA953X_TYPE: 463 case PCA953X_TYPE:
@@ -420,45 +467,54 @@ static u32 pca953x_irq_pending(struct pca953x_chip *chip)
420 offset = PCA957X_IN; 467 offset = PCA957X_IN;
421 break; 468 break;
422 } 469 }
423 ret = pca953x_read_reg(chip, offset, &cur_stat); 470 ret = pca953x_read_regs(chip, offset, cur_stat);
424 if (ret) 471 if (ret)
425 return 0; 472 return 0;
426 473
427 /* Remove output pins from the equation */ 474 /* Remove output pins from the equation */
428 cur_stat &= chip->reg_direction; 475 for (i = 0; i < NBANK(chip); i++)
476 cur_stat[i] &= chip->reg_direction[i];
429 477
430 old_stat = chip->irq_stat; 478 memcpy(old_stat, chip->irq_stat, NBANK(chip));
431 trigger = (cur_stat ^ old_stat) & chip->irq_mask;
432 479
433 if (!trigger) 480 for (i = 0; i < NBANK(chip); i++) {
481 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
482 triggers += trigger[i];
483 }
484
485 if (!triggers)
434 return 0; 486 return 0;
435 487
436 chip->irq_stat = cur_stat; 488 memcpy(chip->irq_stat, cur_stat, NBANK(chip));
437 489
438 pending = (old_stat & chip->irq_trig_fall) | 490 for (i = 0; i < NBANK(chip); i++) {
439 (cur_stat & chip->irq_trig_raise); 491 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
440 pending &= trigger; 492 (cur_stat[i] & chip->irq_trig_raise[i]);
493 pending[i] &= trigger[i];
494 pendings += pending[i];
495 }
441 496
442 return pending; 497 return pendings;
443} 498}
444 499
445static irqreturn_t pca953x_irq_handler(int irq, void *devid) 500static irqreturn_t pca953x_irq_handler(int irq, void *devid)
446{ 501{
447 struct pca953x_chip *chip = devid; 502 struct pca953x_chip *chip = devid;
448 u32 pending; 503 u8 pending[MAX_BANK];
449 u32 level; 504 u8 level;
450 505 int i;
451 pending = pca953x_irq_pending(chip);
452 506
453 if (!pending) 507 if (!pca953x_irq_pending(chip, pending))
454 return IRQ_HANDLED; 508 return IRQ_HANDLED;
455 509
456 do { 510 for (i = 0; i < NBANK(chip); i++) {
457 level = __ffs(pending); 511 while (pending[i]) {
458 handle_nested_irq(irq_find_mapping(chip->domain, level)); 512 level = __ffs(pending[i]);
459 513 handle_nested_irq(irq_find_mapping(chip->domain,
460 pending &= ~(1 << level); 514 level + (BANK_SZ * i)));
461 } while (pending); 515 pending[i] &= ~(1 << level);
516 }
517 }
462 518
463 return IRQ_HANDLED; 519 return IRQ_HANDLED;
464} 520}
@@ -468,8 +524,7 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
468 int irq_base) 524 int irq_base)
469{ 525{
470 struct i2c_client *client = chip->client; 526 struct i2c_client *client = chip->client;
471 int ret, offset = 0; 527 int ret, i, offset = 0;
472 u32 temporary;
473 528
474 if (irq_base != -1 529 if (irq_base != -1
475 && (id->driver_data & PCA_INT)) { 530 && (id->driver_data & PCA_INT)) {
@@ -483,8 +538,7 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
483 offset = PCA957X_IN; 538 offset = PCA957X_IN;
484 break; 539 break;
485 } 540 }
486 ret = pca953x_read_reg(chip, offset, &temporary); 541 ret = pca953x_read_regs(chip, offset, chip->irq_stat);
487 chip->irq_stat = temporary;
488 if (ret) 542 if (ret)
489 goto out_failed; 543 goto out_failed;
490 544
@@ -493,7 +547,8 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
493 * interrupt. We have to rely on the previous read for 547 * interrupt. We have to rely on the previous read for
494 * this purpose. 548 * this purpose.
495 */ 549 */
496 chip->irq_stat &= chip->reg_direction; 550 for (i = 0; i < NBANK(chip); i++)
551 chip->irq_stat[i] &= chip->reg_direction[i];
497 mutex_init(&chip->irq_lock); 552 mutex_init(&chip->irq_lock);
498 553
499 chip->irq_base = irq_alloc_descs(-1, irq_base, chip->gpio_chip.ngpio, -1); 554 chip->irq_base = irq_alloc_descs(-1, irq_base, chip->gpio_chip.ngpio, -1);
@@ -619,18 +674,24 @@ pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
619static int device_pca953x_init(struct pca953x_chip *chip, u32 invert) 674static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
620{ 675{
621 int ret; 676 int ret;
677 u8 val[MAX_BANK];
622 678
623 ret = pca953x_read_reg(chip, PCA953X_OUTPUT, &chip->reg_output); 679 ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
624 if (ret) 680 if (ret)
625 goto out; 681 goto out;
626 682
627 ret = pca953x_read_reg(chip, PCA953X_DIRECTION, 683 ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
628 &chip->reg_direction); 684 chip->reg_direction);
629 if (ret) 685 if (ret)
630 goto out; 686 goto out;
631 687
632 /* set platform specific polarity inversion */ 688 /* set platform specific polarity inversion */
633 ret = pca953x_write_reg(chip, PCA953X_INVERT, invert); 689 if (invert)
690 memset(val, 0xFF, NBANK(chip));
691 else
692 memset(val, 0, NBANK(chip));
693
694 ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
634out: 695out:
635 return ret; 696 return ret;
636} 697}
@@ -638,28 +699,36 @@ out:
638static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) 699static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
639{ 700{
640 int ret; 701 int ret;
641 u32 val = 0; 702 u8 val[MAX_BANK];
642 703
643 /* Let every port in proper state, that could save power */ 704 /* Let every port in proper state, that could save power */
644 pca953x_write_reg(chip, PCA957X_PUPD, 0x0); 705 memset(val, 0, NBANK(chip));
645 pca953x_write_reg(chip, PCA957X_CFG, 0xffff); 706 pca953x_write_regs(chip, PCA957X_PUPD, val);
646 pca953x_write_reg(chip, PCA957X_OUT, 0x0); 707 memset(val, 0xFF, NBANK(chip));
647 708 pca953x_write_regs(chip, PCA957X_CFG, val);
648 ret = pca953x_read_reg(chip, PCA957X_IN, &val); 709 memset(val, 0, NBANK(chip));
710 pca953x_write_regs(chip, PCA957X_OUT, val);
711
712 ret = pca953x_read_regs(chip, PCA957X_IN, val);
649 if (ret) 713 if (ret)
650 goto out; 714 goto out;
651 ret = pca953x_read_reg(chip, PCA957X_OUT, &chip->reg_output); 715 ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
652 if (ret) 716 if (ret)
653 goto out; 717 goto out;
654 ret = pca953x_read_reg(chip, PCA957X_CFG, &chip->reg_direction); 718 ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
655 if (ret) 719 if (ret)
656 goto out; 720 goto out;
657 721
658 /* set platform specific polarity inversion */ 722 /* set platform specific polarity inversion */
659 pca953x_write_reg(chip, PCA957X_INVRT, invert); 723 if (invert)
724 memset(val, 0xFF, NBANK(chip));
725 else
726 memset(val, 0, NBANK(chip));
727 pca953x_write_regs(chip, PCA957X_INVRT, val);
660 728
661 /* To enable register 6, 7 to controll pull up and pull down */ 729 /* To enable register 6, 7 to controll pull up and pull down */
662 pca953x_write_reg(chip, PCA957X_BKEN, 0x202); 730 memset(val, 0x02, NBANK(chip));
731 pca953x_write_regs(chip, PCA957X_BKEN, val);
663 732
664 return 0; 733 return 0;
665out: 734out: