diff options
author | Takashi Iwai <tiwai@suse.de> | 2013-10-25 05:43:47 -0400 |
---|---|---|
committer | Takashi Iwai <tiwai@suse.de> | 2013-10-25 05:43:47 -0400 |
commit | 6913a9dbf18f08e3577695032da15812bda92b66 (patch) | |
tree | 05ca8620b11f2898022a7fd8a00f1f8566161428 /drivers/gpio/gpio-omap.c | |
parent | 7342017f4a0f129d277f78b8761f2732661ba30a (diff) | |
parent | 9645083ca5ef365b7b750cf219bb20b61bb925f8 (diff) |
Merge tag 'asoc-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next
ASoC: Updates for v3.13
- Further work on the dmaengine helpers, including support for
configuring the parameters for DMA by reading the capabilities of the
DMA controller which removes some guesswork and magic numbers fromm
drivers.
- A refresh of the documentation.
- Conversions of many drivers to direct regmap API usage in order to
allow the ASoC level register I/O code to be removed, this will
hopefully be completed by v3.14.
- Support for using async register I/O in DAPM, reducing the time taken
to implement power transitions on systems that support it.
Diffstat (limited to 'drivers/gpio/gpio-omap.c')
-rw-r--r-- | drivers/gpio/gpio-omap.c | 158 |
1 files changed, 101 insertions, 57 deletions
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 0ff43552d472..89675f862308 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c | |||
@@ -63,6 +63,7 @@ struct gpio_bank { | |||
63 | struct gpio_chip chip; | 63 | struct gpio_chip chip; |
64 | struct clk *dbck; | 64 | struct clk *dbck; |
65 | u32 mod_usage; | 65 | u32 mod_usage; |
66 | u32 irq_usage; | ||
66 | u32 dbck_enable_mask; | 67 | u32 dbck_enable_mask; |
67 | bool dbck_enabled; | 68 | bool dbck_enabled; |
68 | struct device *dev; | 69 | struct device *dev; |
@@ -86,6 +87,9 @@ struct gpio_bank { | |||
86 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | 87 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) |
87 | #define GPIO_MOD_CTRL_BIT BIT(0) | 88 | #define GPIO_MOD_CTRL_BIT BIT(0) |
88 | 89 | ||
90 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) | ||
91 | #define LINE_USED(line, offset) (line & (1 << offset)) | ||
92 | |||
89 | static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq) | 93 | static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq) |
90 | { | 94 | { |
91 | return bank->chip.base + gpio_irq; | 95 | return bank->chip.base + gpio_irq; |
@@ -420,15 +424,69 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, | |||
420 | return 0; | 424 | return 0; |
421 | } | 425 | } |
422 | 426 | ||
427 | static void _enable_gpio_module(struct gpio_bank *bank, unsigned offset) | ||
428 | { | ||
429 | if (bank->regs->pinctrl) { | ||
430 | void __iomem *reg = bank->base + bank->regs->pinctrl; | ||
431 | |||
432 | /* Claim the pin for MPU */ | ||
433 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); | ||
434 | } | ||
435 | |||
436 | if (bank->regs->ctrl && !BANK_USED(bank)) { | ||
437 | void __iomem *reg = bank->base + bank->regs->ctrl; | ||
438 | u32 ctrl; | ||
439 | |||
440 | ctrl = __raw_readl(reg); | ||
441 | /* Module is enabled, clocks are not gated */ | ||
442 | ctrl &= ~GPIO_MOD_CTRL_BIT; | ||
443 | __raw_writel(ctrl, reg); | ||
444 | bank->context.ctrl = ctrl; | ||
445 | } | ||
446 | } | ||
447 | |||
448 | static void _disable_gpio_module(struct gpio_bank *bank, unsigned offset) | ||
449 | { | ||
450 | void __iomem *base = bank->base; | ||
451 | |||
452 | if (bank->regs->wkup_en && | ||
453 | !LINE_USED(bank->mod_usage, offset) && | ||
454 | !LINE_USED(bank->irq_usage, offset)) { | ||
455 | /* Disable wake-up during idle for dynamic tick */ | ||
456 | _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0); | ||
457 | bank->context.wake_en = | ||
458 | __raw_readl(bank->base + bank->regs->wkup_en); | ||
459 | } | ||
460 | |||
461 | if (bank->regs->ctrl && !BANK_USED(bank)) { | ||
462 | void __iomem *reg = bank->base + bank->regs->ctrl; | ||
463 | u32 ctrl; | ||
464 | |||
465 | ctrl = __raw_readl(reg); | ||
466 | /* Module is disabled, clocks are gated */ | ||
467 | ctrl |= GPIO_MOD_CTRL_BIT; | ||
468 | __raw_writel(ctrl, reg); | ||
469 | bank->context.ctrl = ctrl; | ||
470 | } | ||
471 | } | ||
472 | |||
473 | static int gpio_is_input(struct gpio_bank *bank, int mask) | ||
474 | { | ||
475 | void __iomem *reg = bank->base + bank->regs->direction; | ||
476 | |||
477 | return __raw_readl(reg) & mask; | ||
478 | } | ||
479 | |||
423 | static int gpio_irq_type(struct irq_data *d, unsigned type) | 480 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
424 | { | 481 | { |
425 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | 482 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
426 | unsigned gpio = 0; | 483 | unsigned gpio = 0; |
427 | int retval; | 484 | int retval; |
428 | unsigned long flags; | 485 | unsigned long flags; |
486 | unsigned offset; | ||
429 | 487 | ||
430 | if (WARN_ON(!bank->mod_usage)) | 488 | if (!BANK_USED(bank)) |
431 | return -EINVAL; | 489 | pm_runtime_get_sync(bank->dev); |
432 | 490 | ||
433 | #ifdef CONFIG_ARCH_OMAP1 | 491 | #ifdef CONFIG_ARCH_OMAP1 |
434 | if (d->irq > IH_MPUIO_BASE) | 492 | if (d->irq > IH_MPUIO_BASE) |
@@ -446,7 +504,17 @@ static int gpio_irq_type(struct irq_data *d, unsigned type) | |||
446 | return -EINVAL; | 504 | return -EINVAL; |
447 | 505 | ||
448 | spin_lock_irqsave(&bank->lock, flags); | 506 | spin_lock_irqsave(&bank->lock, flags); |
449 | retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); | 507 | offset = GPIO_INDEX(bank, gpio); |
508 | retval = _set_gpio_triggering(bank, offset, type); | ||
509 | if (!LINE_USED(bank->mod_usage, offset)) { | ||
510 | _enable_gpio_module(bank, offset); | ||
511 | _set_gpio_direction(bank, offset, 1); | ||
512 | } else if (!gpio_is_input(bank, 1 << offset)) { | ||
513 | spin_unlock_irqrestore(&bank->lock, flags); | ||
514 | return -EINVAL; | ||
515 | } | ||
516 | |||
517 | bank->irq_usage |= 1 << GPIO_INDEX(bank, gpio); | ||
450 | spin_unlock_irqrestore(&bank->lock, flags); | 518 | spin_unlock_irqrestore(&bank->lock, flags); |
451 | 519 | ||
452 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | 520 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
@@ -603,35 +671,19 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) | |||
603 | * If this is the first gpio_request for the bank, | 671 | * If this is the first gpio_request for the bank, |
604 | * enable the bank module. | 672 | * enable the bank module. |
605 | */ | 673 | */ |
606 | if (!bank->mod_usage) | 674 | if (!BANK_USED(bank)) |
607 | pm_runtime_get_sync(bank->dev); | 675 | pm_runtime_get_sync(bank->dev); |
608 | 676 | ||
609 | spin_lock_irqsave(&bank->lock, flags); | 677 | spin_lock_irqsave(&bank->lock, flags); |
610 | /* Set trigger to none. You need to enable the desired trigger with | 678 | /* Set trigger to none. You need to enable the desired trigger with |
611 | * request_irq() or set_irq_type(). | 679 | * request_irq() or set_irq_type(). Only do this if the IRQ line has |
680 | * not already been requested. | ||
612 | */ | 681 | */ |
613 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | 682 | if (!LINE_USED(bank->irq_usage, offset)) { |
614 | 683 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
615 | if (bank->regs->pinctrl) { | 684 | _enable_gpio_module(bank, offset); |
616 | void __iomem *reg = bank->base + bank->regs->pinctrl; | ||
617 | |||
618 | /* Claim the pin for MPU */ | ||
619 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); | ||
620 | } | ||
621 | |||
622 | if (bank->regs->ctrl && !bank->mod_usage) { | ||
623 | void __iomem *reg = bank->base + bank->regs->ctrl; | ||
624 | u32 ctrl; | ||
625 | |||
626 | ctrl = __raw_readl(reg); | ||
627 | /* Module is enabled, clocks are not gated */ | ||
628 | ctrl &= ~GPIO_MOD_CTRL_BIT; | ||
629 | __raw_writel(ctrl, reg); | ||
630 | bank->context.ctrl = ctrl; | ||
631 | } | 685 | } |
632 | |||
633 | bank->mod_usage |= 1 << offset; | 686 | bank->mod_usage |= 1 << offset; |
634 | |||
635 | spin_unlock_irqrestore(&bank->lock, flags); | 687 | spin_unlock_irqrestore(&bank->lock, flags); |
636 | 688 | ||
637 | return 0; | 689 | return 0; |
@@ -640,31 +692,11 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) | |||
640 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) | 692 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
641 | { | 693 | { |
642 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); | 694 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
643 | void __iomem *base = bank->base; | ||
644 | unsigned long flags; | 695 | unsigned long flags; |
645 | 696 | ||
646 | spin_lock_irqsave(&bank->lock, flags); | 697 | spin_lock_irqsave(&bank->lock, flags); |
647 | |||
648 | if (bank->regs->wkup_en) { | ||
649 | /* Disable wake-up during idle for dynamic tick */ | ||
650 | _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0); | ||
651 | bank->context.wake_en = | ||
652 | __raw_readl(bank->base + bank->regs->wkup_en); | ||
653 | } | ||
654 | |||
655 | bank->mod_usage &= ~(1 << offset); | 698 | bank->mod_usage &= ~(1 << offset); |
656 | 699 | _disable_gpio_module(bank, offset); | |
657 | if (bank->regs->ctrl && !bank->mod_usage) { | ||
658 | void __iomem *reg = bank->base + bank->regs->ctrl; | ||
659 | u32 ctrl; | ||
660 | |||
661 | ctrl = __raw_readl(reg); | ||
662 | /* Module is disabled, clocks are gated */ | ||
663 | ctrl |= GPIO_MOD_CTRL_BIT; | ||
664 | __raw_writel(ctrl, reg); | ||
665 | bank->context.ctrl = ctrl; | ||
666 | } | ||
667 | |||
668 | _reset_gpio(bank, bank->chip.base + offset); | 700 | _reset_gpio(bank, bank->chip.base + offset); |
669 | spin_unlock_irqrestore(&bank->lock, flags); | 701 | spin_unlock_irqrestore(&bank->lock, flags); |
670 | 702 | ||
@@ -672,7 +704,7 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) | |||
672 | * If this is the last gpio to be freed in the bank, | 704 | * If this is the last gpio to be freed in the bank, |
673 | * disable the bank module. | 705 | * disable the bank module. |
674 | */ | 706 | */ |
675 | if (!bank->mod_usage) | 707 | if (!BANK_USED(bank)) |
676 | pm_runtime_put(bank->dev); | 708 | pm_runtime_put(bank->dev); |
677 | } | 709 | } |
678 | 710 | ||
@@ -762,10 +794,20 @@ static void gpio_irq_shutdown(struct irq_data *d) | |||
762 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | 794 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
763 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); | 795 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
764 | unsigned long flags; | 796 | unsigned long flags; |
797 | unsigned offset = GPIO_INDEX(bank, gpio); | ||
765 | 798 | ||
766 | spin_lock_irqsave(&bank->lock, flags); | 799 | spin_lock_irqsave(&bank->lock, flags); |
800 | bank->irq_usage &= ~(1 << offset); | ||
801 | _disable_gpio_module(bank, offset); | ||
767 | _reset_gpio(bank, gpio); | 802 | _reset_gpio(bank, gpio); |
768 | spin_unlock_irqrestore(&bank->lock, flags); | 803 | spin_unlock_irqrestore(&bank->lock, flags); |
804 | |||
805 | /* | ||
806 | * If this is the last IRQ to be freed in the bank, | ||
807 | * disable the bank module. | ||
808 | */ | ||
809 | if (!BANK_USED(bank)) | ||
810 | pm_runtime_put(bank->dev); | ||
769 | } | 811 | } |
770 | 812 | ||
771 | static void gpio_ack_irq(struct irq_data *d) | 813 | static void gpio_ack_irq(struct irq_data *d) |
@@ -897,13 +939,6 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset) | |||
897 | return 0; | 939 | return 0; |
898 | } | 940 | } |
899 | 941 | ||
900 | static int gpio_is_input(struct gpio_bank *bank, int mask) | ||
901 | { | ||
902 | void __iomem *reg = bank->base + bank->regs->direction; | ||
903 | |||
904 | return __raw_readl(reg) & mask; | ||
905 | } | ||
906 | |||
907 | static int gpio_get(struct gpio_chip *chip, unsigned offset) | 942 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
908 | { | 943 | { |
909 | struct gpio_bank *bank; | 944 | struct gpio_bank *bank; |
@@ -922,13 +957,22 @@ static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |||
922 | { | 957 | { |
923 | struct gpio_bank *bank; | 958 | struct gpio_bank *bank; |
924 | unsigned long flags; | 959 | unsigned long flags; |
960 | int retval = 0; | ||
925 | 961 | ||
926 | bank = container_of(chip, struct gpio_bank, chip); | 962 | bank = container_of(chip, struct gpio_bank, chip); |
927 | spin_lock_irqsave(&bank->lock, flags); | 963 | spin_lock_irqsave(&bank->lock, flags); |
964 | |||
965 | if (LINE_USED(bank->irq_usage, offset)) { | ||
966 | retval = -EINVAL; | ||
967 | goto exit; | ||
968 | } | ||
969 | |||
928 | bank->set_dataout(bank, offset, value); | 970 | bank->set_dataout(bank, offset, value); |
929 | _set_gpio_direction(bank, offset, 0); | 971 | _set_gpio_direction(bank, offset, 0); |
972 | |||
973 | exit: | ||
930 | spin_unlock_irqrestore(&bank->lock, flags); | 974 | spin_unlock_irqrestore(&bank->lock, flags); |
931 | return 0; | 975 | return retval; |
932 | } | 976 | } |
933 | 977 | ||
934 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, | 978 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
@@ -1400,7 +1444,7 @@ void omap2_gpio_prepare_for_idle(int pwr_mode) | |||
1400 | struct gpio_bank *bank; | 1444 | struct gpio_bank *bank; |
1401 | 1445 | ||
1402 | list_for_each_entry(bank, &omap_gpio_list, node) { | 1446 | list_for_each_entry(bank, &omap_gpio_list, node) { |
1403 | if (!bank->mod_usage || !bank->loses_context) | 1447 | if (!BANK_USED(bank) || !bank->loses_context) |
1404 | continue; | 1448 | continue; |
1405 | 1449 | ||
1406 | bank->power_mode = pwr_mode; | 1450 | bank->power_mode = pwr_mode; |
@@ -1414,7 +1458,7 @@ void omap2_gpio_resume_after_idle(void) | |||
1414 | struct gpio_bank *bank; | 1458 | struct gpio_bank *bank; |
1415 | 1459 | ||
1416 | list_for_each_entry(bank, &omap_gpio_list, node) { | 1460 | list_for_each_entry(bank, &omap_gpio_list, node) { |
1417 | if (!bank->mod_usage || !bank->loses_context) | 1461 | if (!BANK_USED(bank) || !bank->loses_context) |
1418 | continue; | 1462 | continue; |
1419 | 1463 | ||
1420 | pm_runtime_get_sync(bank->dev); | 1464 | pm_runtime_get_sync(bank->dev); |