diff options
author | Feng Tang <feng.tang@intel.com> | 2011-12-13 10:53:50 -0500 |
---|---|---|
committer | Grant Likely <grant.likely@secretlab.ca> | 2011-12-13 13:05:17 -0500 |
commit | 4d052213ff8f71a4a70fc4eed71b773cfde51fcf (patch) | |
tree | 5b4174022eadbf3327f59d9046f1ac3a4bd9e821 /drivers/gpio/gpio-ml-ioh.c | |
parent | f9ea14efa5277c47efec341dee2c408b6b80f854 (diff) |
gpio-ml-ioh: Add the irq_disable/irq_enable hooks for ml-ioh irq chip
These hooks will be needed by the general disabl/enable_irq();
Signed-off-by: Feng Tang <feng.tang@intel.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/gpio/gpio-ml-ioh.c')
-rw-r--r-- | drivers/gpio/gpio-ml-ioh.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/gpio/gpio-ml-ioh.c b/drivers/gpio/gpio-ml-ioh.c index 92b6f51a206e..461958fc2264 100644 --- a/drivers/gpio/gpio-ml-ioh.c +++ b/drivers/gpio/gpio-ml-ioh.c | |||
@@ -332,6 +332,34 @@ static void ioh_irq_mask(struct irq_data *d) | |||
332 | &chip->reg->regs[chip->ch].imask); | 332 | &chip->reg->regs[chip->ch].imask); |
333 | } | 333 | } |
334 | 334 | ||
335 | static void ioh_irq_disable(struct irq_data *d) | ||
336 | { | ||
337 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | ||
338 | struct ioh_gpio *chip = gc->private; | ||
339 | unsigned long flags; | ||
340 | u32 ien; | ||
341 | |||
342 | spin_lock_irqsave(&chip->spinlock, flags); | ||
343 | ien = ioread32(&chip->reg->regs[chip->ch].ien); | ||
344 | ien &= ~(1 << (d->irq - chip->irq_base)); | ||
345 | iowrite32(ien, &chip->reg->regs[chip->ch].ien); | ||
346 | spin_unlock_irqrestore(&chip->spinlock, flags); | ||
347 | } | ||
348 | |||
349 | static void ioh_irq_enable(struct irq_data *d) | ||
350 | { | ||
351 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | ||
352 | struct ioh_gpio *chip = gc->private; | ||
353 | unsigned long flags; | ||
354 | u32 ien; | ||
355 | |||
356 | spin_lock_irqsave(&chip->spinlock, flags); | ||
357 | ien = ioread32(&chip->reg->regs[chip->ch].ien); | ||
358 | ien |= 1 << (d->irq - chip->irq_base); | ||
359 | iowrite32(ien, &chip->reg->regs[chip->ch].ien); | ||
360 | spin_unlock_irqrestore(&chip->spinlock, flags); | ||
361 | } | ||
362 | |||
335 | static irqreturn_t ioh_gpio_handler(int irq, void *dev_id) | 363 | static irqreturn_t ioh_gpio_handler(int irq, void *dev_id) |
336 | { | 364 | { |
337 | struct ioh_gpio *chip = dev_id; | 365 | struct ioh_gpio *chip = dev_id; |
@@ -370,6 +398,8 @@ static __devinit void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip, | |||
370 | ct->chip.irq_mask = ioh_irq_mask; | 398 | ct->chip.irq_mask = ioh_irq_mask; |
371 | ct->chip.irq_unmask = ioh_irq_unmask; | 399 | ct->chip.irq_unmask = ioh_irq_unmask; |
372 | ct->chip.irq_set_type = ioh_irq_type; | 400 | ct->chip.irq_set_type = ioh_irq_type; |
401 | ct->chip.irq_disable = ioh_irq_disable; | ||
402 | ct->chip.irq_enable = ioh_irq_enable; | ||
373 | 403 | ||
374 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | 404 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, |
375 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | 405 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); |