aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpio/gpio-lynxpoint.c
diff options
context:
space:
mode:
authorMika Westerberg <mika.westerberg@linux.intel.com>2013-10-01 10:35:43 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-10-11 07:16:32 -0400
commit03d152d5582abc8a1c19cb107164c3724bbd4be4 (patch)
tree2461725bde10d4d9fdb0e057d476df1ccffbe5dd /drivers/gpio/gpio-lynxpoint.c
parentd0e639c9e06d44e713170031fe05fb60ebe680af (diff)
gpio/lynxpoint: check if the interrupt is enabled in IRQ handler
Checking LP_INT_STAT is not enough in the interrupt handler because its contents get updated regardless of whether the pin has interrupt enabled or not. This causes the driver to loop forever for GPIOs that are pulled up. Fix this by checking the interrupt enable bit for the pin as well. Cc: stable@vger.kernel.org Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/gpio/gpio-lynxpoint.c')
-rw-r--r--drivers/gpio/gpio-lynxpoint.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpio/gpio-lynxpoint.c b/drivers/gpio/gpio-lynxpoint.c
index 2d9ca6055e5e..41b5913ddabe 100644
--- a/drivers/gpio/gpio-lynxpoint.c
+++ b/drivers/gpio/gpio-lynxpoint.c
@@ -248,14 +248,15 @@ static void lp_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
248 struct lp_gpio *lg = irq_data_get_irq_handler_data(data); 248 struct lp_gpio *lg = irq_data_get_irq_handler_data(data);
249 struct irq_chip *chip = irq_data_get_irq_chip(data); 249 struct irq_chip *chip = irq_data_get_irq_chip(data);
250 u32 base, pin, mask; 250 u32 base, pin, mask;
251 unsigned long reg, pending; 251 unsigned long reg, ena, pending;
252 unsigned virq; 252 unsigned virq;
253 253
254 /* check from GPIO controller which pin triggered the interrupt */ 254 /* check from GPIO controller which pin triggered the interrupt */
255 for (base = 0; base < lg->chip.ngpio; base += 32) { 255 for (base = 0; base < lg->chip.ngpio; base += 32) {
256 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 256 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
257 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
257 258
258 while ((pending = inl(reg))) { 259 while ((pending = (inl(reg) & inl(ena)))) {
259 pin = __ffs(pending); 260 pin = __ffs(pending);
260 mask = BIT(pin); 261 mask = BIT(pin);
261 /* Clear before handling so we don't lose an edge */ 262 /* Clear before handling so we don't lose an edge */