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authorMika Westerberg <mika.westerberg@linux.intel.com>2012-04-05 05:15:17 -0400
committerGrant Likely <grant.likely@secretlab.ca>2012-04-06 00:39:02 -0400
commitf5f93117f4ac24b8493cda67e6a1443517d26845 (patch)
tree0245bf2c9947ec40d82aaae81be5ecede22bfa29 /drivers/gpio/gpio-langwell.c
parentb3e35af2b0ea9ad1618e01f40a1ffee83333ef35 (diff)
gpio/langwell: clear IRQ edge detect registers at init
The boot firmware might leave the registers configured causing interrupts to happen even when no handler for them is yet registered. Fix this by clearing the IRQ edge detect registers at init. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/gpio/gpio-langwell.c')
-rw-r--r--drivers/gpio/gpio-langwell.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/gpio/gpio-langwell.c b/drivers/gpio/gpio-langwell.c
index bc15ae3d7cf2..52f00d3cf667 100644
--- a/drivers/gpio/gpio-langwell.c
+++ b/drivers/gpio/gpio-langwell.c
@@ -263,6 +263,24 @@ static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
263 chip->irq_eoi(data); 263 chip->irq_eoi(data);
264} 264}
265 265
266static void lnw_irq_init_hw(struct lnw_gpio *lnw)
267{
268 void __iomem *reg;
269 unsigned base;
270
271 for (base = 0; base < lnw->chip.ngpio; base += 32) {
272 /* Clear the rising-edge detect register */
273 reg = gpio_reg(&lnw->chip, base, GRER);
274 writel(0, reg);
275 /* Clear the falling-edge detect register */
276 reg = gpio_reg(&lnw->chip, base, GFER);
277 writel(0, reg);
278 /* Clear the edge detect status register */
279 reg = gpio_reg(&lnw->chip, base, GEDR);
280 writel(~0, reg);
281 }
282}
283
266#ifdef CONFIG_PM 284#ifdef CONFIG_PM
267static int lnw_gpio_runtime_resume(struct device *dev) 285static int lnw_gpio_runtime_resume(struct device *dev)
268{ 286{
@@ -371,6 +389,9 @@ static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
371 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval); 389 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
372 goto err4; 390 goto err4;
373 } 391 }
392
393 lnw_irq_init_hw(lnw);
394
374 irq_set_handler_data(pdev->irq, lnw); 395 irq_set_handler_data(pdev->irq, lnw);
375 irq_set_chained_handler(pdev->irq, lnw_irq_handler); 396 irq_set_chained_handler(pdev->irq, lnw_irq_handler);
376 for (i = 0; i < lnw->chip.ngpio; i++) { 397 for (i = 0; i < lnw->chip.ngpio; i++) {