diff options
author | Jay Fenlason <fenlason@redhat.com> | 2009-11-17 12:29:17 -0500 |
---|---|---|
committer | Stefan Richter <stefanr@s5r6.in-berlin.de> | 2009-11-18 14:31:17 -0500 |
commit | 5ed1f321a71b8549cc2eea26c94fe7943ed01d31 (patch) | |
tree | c27a802d0feed854a4842805d041bcb44d362f10 /drivers/firewire | |
parent | eaf76e0d027a917a013ad8a88a94132d0feab622 (diff) |
firewire: ohci: Make cycleMatch ISO transmission work
Calling the START_ISO ioctl with a nonnegative cycle paramater has
never worked. Last night I got around to figuring out why. Most of
this patch is a big comment explaining why we enable an interrupt
source then don't actually do anything when we get one. As the
comment says, we should do more, but we don't have a way to tell
userspace what happened. . .
Signed-off-by: Jay Fenlason <fenlason@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de> (edited comment)
Diffstat (limited to 'drivers/firewire')
-rw-r--r-- | drivers/firewire/ohci.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c index 5d524254499e..c07cfada190a 100644 --- a/drivers/firewire/ohci.c +++ b/drivers/firewire/ohci.c | |||
@@ -275,7 +275,7 @@ static void log_irqs(u32 evt) | |||
275 | !(evt & OHCI1394_busReset)) | 275 | !(evt & OHCI1394_busReset)) |
276 | return; | 276 | return; |
277 | 277 | ||
278 | fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, | 278 | fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, |
279 | evt & OHCI1394_selfIDComplete ? " selfID" : "", | 279 | evt & OHCI1394_selfIDComplete ? " selfID" : "", |
280 | evt & OHCI1394_RQPkt ? " AR_req" : "", | 280 | evt & OHCI1394_RQPkt ? " AR_req" : "", |
281 | evt & OHCI1394_RSPkt ? " AR_resp" : "", | 281 | evt & OHCI1394_RSPkt ? " AR_resp" : "", |
@@ -286,6 +286,7 @@ static void log_irqs(u32 evt) | |||
286 | evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", | 286 | evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", |
287 | evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", | 287 | evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", |
288 | evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", | 288 | evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", |
289 | evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", | ||
289 | evt & OHCI1394_regAccessFail ? " regAccessFail" : "", | 290 | evt & OHCI1394_regAccessFail ? " regAccessFail" : "", |
290 | evt & OHCI1394_busReset ? " busReset" : "", | 291 | evt & OHCI1394_busReset ? " busReset" : "", |
291 | evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | | 292 | evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | |
@@ -293,6 +294,7 @@ static void log_irqs(u32 evt) | |||
293 | OHCI1394_respTxComplete | OHCI1394_isochRx | | 294 | OHCI1394_respTxComplete | OHCI1394_isochRx | |
294 | OHCI1394_isochTx | OHCI1394_postedWriteErr | | 295 | OHCI1394_isochTx | OHCI1394_postedWriteErr | |
295 | OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | | 296 | OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | |
297 | OHCI1394_cycleInconsistent | | ||
296 | OHCI1394_regAccessFail | OHCI1394_busReset) | 298 | OHCI1394_regAccessFail | OHCI1394_busReset) |
297 | ? " ?" : ""); | 299 | ? " ?" : ""); |
298 | } | 300 | } |
@@ -1439,6 +1441,17 @@ static irqreturn_t irq_handler(int irq, void *data) | |||
1439 | OHCI1394_LinkControl_cycleMaster); | 1441 | OHCI1394_LinkControl_cycleMaster); |
1440 | } | 1442 | } |
1441 | 1443 | ||
1444 | if (unlikely(event & OHCI1394_cycleInconsistent)) { | ||
1445 | /* | ||
1446 | * We need to clear this event bit in order to make | ||
1447 | * cycleMatch isochronous I/O work. In theory we should | ||
1448 | * stop active cycleMatch iso contexts now and restart | ||
1449 | * them at least two cycles later. (FIXME?) | ||
1450 | */ | ||
1451 | if (printk_ratelimit()) | ||
1452 | fw_notify("isochronous cycle inconsistent\n"); | ||
1453 | } | ||
1454 | |||
1442 | if (event & OHCI1394_cycle64Seconds) { | 1455 | if (event & OHCI1394_cycle64Seconds) { |
1443 | cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | 1456 | cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); |
1444 | if ((cycle_time & 0x80000000) == 0) | 1457 | if ((cycle_time & 0x80000000) == 0) |
@@ -1528,6 +1541,7 @@ static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) | |||
1528 | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | | 1541 | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | |
1529 | OHCI1394_isochRx | OHCI1394_isochTx | | 1542 | OHCI1394_isochRx | OHCI1394_isochTx | |
1530 | OHCI1394_postedWriteErr | OHCI1394_cycleTooLong | | 1543 | OHCI1394_postedWriteErr | OHCI1394_cycleTooLong | |
1544 | OHCI1394_cycleInconsistent | | ||
1531 | OHCI1394_cycle64Seconds | OHCI1394_regAccessFail | | 1545 | OHCI1394_cycle64Seconds | OHCI1394_regAccessFail | |
1532 | OHCI1394_masterIntEnable); | 1546 | OHCI1394_masterIntEnable); |
1533 | if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) | 1547 | if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) |