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author | Stefan Richter <stefanr@s5r6.in-berlin.de> | 2010-07-27 04:28:30 -0400 |
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committer | Stefan Richter <stefanr@s5r6.in-berlin.de> | 2010-07-27 05:04:10 -0400 |
commit | b5e47729043c9224b21ab3dc7c63e8a38dbb4923 (patch) | |
tree | 2acf6aa0f441c3a6b8812c8c5eb3b97a74f98056 /drivers/firewire/nosy.h | |
parent | 286468210d83ce0ca1e37e346ed9f4457a161650 (diff) |
firewire: nosy: misc cleanups
Extend copyright note to 2007, c.f. Kristian's git log.
Includes:
- replace some <asm/*.h> by <linux/*.h>
- add required indirectly included <linux/spinlock.h>
- order alphabetically
Coding style related changes:
- change to utf8
- normalize whitespace
- normalize comment style
- remove usages of __FUNCTION__
- remove an unnecessary cast from void *
Const and static declarations:
- driver_name is not const in pci_driver.name, drop const qualifier
- driver_name can be taken from KBUILD_MODNAME
- the global variable minors[] can and should be static
- constify struct file_operations instance
Data types:
- Remove unused struct member struct packet.code. struct packet is
only used for driver-internal bookkeeping; it does not appear on the
wire or in DMA programs or the userspace ABI. Hence the unused
member .code can be removed without worries.
Preprocessor macros:
- unroll a preprocessor macro that containd a return
- use list_for_each_entry
Printk:
- add missing terminating \n in some format strings
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
Diffstat (limited to 'drivers/firewire/nosy.h')
-rw-r--r-- | drivers/firewire/nosy.h | 27 |
1 files changed, 13 insertions, 14 deletions
diff --git a/drivers/firewire/nosy.h b/drivers/firewire/nosy.h index 3440071ac0d2..078ff27f4756 100644 --- a/drivers/firewire/nosy.h +++ b/drivers/firewire/nosy.h | |||
@@ -1,4 +1,5 @@ | |||
1 | /* Chip register definitions for PCILynx chipset. Based on pcilynx.h | 1 | /* |
2 | * Chip register definitions for PCILynx chipset. Based on pcilynx.h | ||
2 | * from the Linux 1394 drivers, but modified a bit so the names here | 3 | * from the Linux 1394 drivers, but modified a bit so the names here |
3 | * match the specification exactly (even though they have weird names, | 4 | * match the specification exactly (even though they have weird names, |
4 | * like xxx_OVER_FLOW, or arbitrary abbreviations like SNTRJ for "sent | 5 | * like xxx_OVER_FLOW, or arbitrary abbreviations like SNTRJ for "sent |
@@ -16,7 +17,7 @@ | |||
16 | #define SERIAL_EEPROM_CONTROL 0x44 | 17 | #define SERIAL_EEPROM_CONTROL 0x44 |
17 | 18 | ||
18 | #define PCI_INT_STATUS 0x48 | 19 | #define PCI_INT_STATUS 0x48 |
19 | #define PCI_INT_ENABLE 0x4c | 20 | #define PCI_INT_ENABLE 0x4c |
20 | /* status and enable have identical bit numbers */ | 21 | /* status and enable have identical bit numbers */ |
21 | #define PCI_INT_INT_PEND (1<<31) | 22 | #define PCI_INT_INT_PEND (1<<31) |
22 | #define PCI_INT_FRC_INT (1<<30) | 23 | #define PCI_INT_FRC_INT (1<<30) |
@@ -48,7 +49,7 @@ | |||
48 | #define LBUS_ADDR_SEL_RAM (0x0<<16) | 49 | #define LBUS_ADDR_SEL_RAM (0x0<<16) |
49 | #define LBUS_ADDR_SEL_ROM (0x1<<16) | 50 | #define LBUS_ADDR_SEL_ROM (0x1<<16) |
50 | #define LBUS_ADDR_SEL_AUX (0x2<<16) | 51 | #define LBUS_ADDR_SEL_AUX (0x2<<16) |
51 | #define LBUS_ADDR_SEL_ZV (0x3<<16) | 52 | #define LBUS_ADDR_SEL_ZV (0x3<<16) |
52 | 53 | ||
53 | #define GPIO_CTRL_A 0xb8 | 54 | #define GPIO_CTRL_A 0xb8 |
54 | #define GPIO_CTRL_B 0xbc | 55 | #define GPIO_CTRL_B 0xbc |
@@ -90,14 +91,14 @@ | |||
90 | #define PCL_BIGENDIAN (1<<16) | 91 | #define PCL_BIGENDIAN (1<<16) |
91 | #define PCL_ISOMODE (1<<12) | 92 | #define PCL_ISOMODE (1<<12) |
92 | 93 | ||
93 | #define DMA0_PREV_PCL 0x100 | 94 | #define DMA0_PREV_PCL 0x100 |
94 | #define DMA1_PREV_PCL 0x120 | 95 | #define DMA1_PREV_PCL 0x120 |
95 | #define DMA2_PREV_PCL 0x140 | 96 | #define DMA2_PREV_PCL 0x140 |
96 | #define DMA3_PREV_PCL 0x160 | 97 | #define DMA3_PREV_PCL 0x160 |
97 | #define DMA4_PREV_PCL 0x180 | 98 | #define DMA4_PREV_PCL 0x180 |
98 | #define DMA_PREV_PCL(chan) (DMA_BREG(DMA0_PREV_PCL, chan)) | 99 | #define DMA_PREV_PCL(chan) (DMA_BREG(DMA0_PREV_PCL, chan)) |
99 | 100 | ||
100 | #define DMA0_CURRENT_PCL 0x104 | 101 | #define DMA0_CURRENT_PCL 0x104 |
101 | #define DMA1_CURRENT_PCL 0x124 | 102 | #define DMA1_CURRENT_PCL 0x124 |
102 | #define DMA2_CURRENT_PCL 0x144 | 103 | #define DMA2_CURRENT_PCL 0x144 |
103 | #define DMA3_CURRENT_PCL 0x164 | 104 | #define DMA3_CURRENT_PCL 0x164 |
@@ -118,15 +119,14 @@ | |||
118 | #define DMA_CHAN_STAT_PKTCMPL (1<<27) | 119 | #define DMA_CHAN_STAT_PKTCMPL (1<<27) |
119 | #define DMA_CHAN_STAT_SPECIALACK (1<<14) | 120 | #define DMA_CHAN_STAT_SPECIALACK (1<<14) |
120 | 121 | ||
121 | 122 | #define DMA0_CHAN_CTRL 0x110 | |
122 | #define DMA0_CHAN_CTRL 0x110 | ||
123 | #define DMA1_CHAN_CTRL 0x130 | 123 | #define DMA1_CHAN_CTRL 0x130 |
124 | #define DMA2_CHAN_CTRL 0x150 | 124 | #define DMA2_CHAN_CTRL 0x150 |
125 | #define DMA3_CHAN_CTRL 0x170 | 125 | #define DMA3_CHAN_CTRL 0x170 |
126 | #define DMA4_CHAN_CTRL 0x190 | 126 | #define DMA4_CHAN_CTRL 0x190 |
127 | #define DMA_CHAN_CTRL(chan) (DMA_BREG(DMA0_CHAN_CTRL, chan)) | 127 | #define DMA_CHAN_CTRL(chan) (DMA_BREG(DMA0_CHAN_CTRL, chan)) |
128 | /* CHAN_CTRL registers share bits */ | 128 | /* CHAN_CTRL registers share bits */ |
129 | #define DMA_CHAN_CTRL_ENABLE (1<<31) | 129 | #define DMA_CHAN_CTRL_ENABLE (1<<31) |
130 | #define DMA_CHAN_CTRL_BUSY (1<<30) | 130 | #define DMA_CHAN_CTRL_BUSY (1<<30) |
131 | #define DMA_CHAN_CTRL_LINK (1<<29) | 131 | #define DMA_CHAN_CTRL_LINK (1<<29) |
132 | 132 | ||
@@ -153,28 +153,28 @@ | |||
153 | #define DMA2_WORD0_CMP_VALUE 0xb20 | 153 | #define DMA2_WORD0_CMP_VALUE 0xb20 |
154 | #define DMA3_WORD0_CMP_VALUE 0xb30 | 154 | #define DMA3_WORD0_CMP_VALUE 0xb30 |
155 | #define DMA4_WORD0_CMP_VALUE 0xb40 | 155 | #define DMA4_WORD0_CMP_VALUE 0xb40 |
156 | #define DMA_WORD0_CMP_VALUE(chan) (DMA_SREG(DMA0_WORD0_CMP_VALUE, chan)) | 156 | #define DMA_WORD0_CMP_VALUE(chan) (DMA_SREG(DMA0_WORD0_CMP_VALUE, chan)) |
157 | 157 | ||
158 | #define DMA0_WORD0_CMP_ENABLE 0xb04 | 158 | #define DMA0_WORD0_CMP_ENABLE 0xb04 |
159 | #define DMA1_WORD0_CMP_ENABLE 0xb14 | 159 | #define DMA1_WORD0_CMP_ENABLE 0xb14 |
160 | #define DMA2_WORD0_CMP_ENABLE 0xb24 | 160 | #define DMA2_WORD0_CMP_ENABLE 0xb24 |
161 | #define DMA3_WORD0_CMP_ENABLE 0xb34 | 161 | #define DMA3_WORD0_CMP_ENABLE 0xb34 |
162 | #define DMA4_WORD0_CMP_ENABLE 0xb44 | 162 | #define DMA4_WORD0_CMP_ENABLE 0xb44 |
163 | #define DMA_WORD0_CMP_ENABLE(chan) (DMA_SREG(DMA0_WORD0_CMP_ENABLE,chan)) | 163 | #define DMA_WORD0_CMP_ENABLE(chan) (DMA_SREG(DMA0_WORD0_CMP_ENABLE, chan)) |
164 | 164 | ||
165 | #define DMA0_WORD1_CMP_VALUE 0xb08 | 165 | #define DMA0_WORD1_CMP_VALUE 0xb08 |
166 | #define DMA1_WORD1_CMP_VALUE 0xb18 | 166 | #define DMA1_WORD1_CMP_VALUE 0xb18 |
167 | #define DMA2_WORD1_CMP_VALUE 0xb28 | 167 | #define DMA2_WORD1_CMP_VALUE 0xb28 |
168 | #define DMA3_WORD1_CMP_VALUE 0xb38 | 168 | #define DMA3_WORD1_CMP_VALUE 0xb38 |
169 | #define DMA4_WORD1_CMP_VALUE 0xb48 | 169 | #define DMA4_WORD1_CMP_VALUE 0xb48 |
170 | #define DMA_WORD1_CMP_VALUE(chan) (DMA_SREG(DMA0_WORD1_CMP_VALUE, chan)) | 170 | #define DMA_WORD1_CMP_VALUE(chan) (DMA_SREG(DMA0_WORD1_CMP_VALUE, chan)) |
171 | 171 | ||
172 | #define DMA0_WORD1_CMP_ENABLE 0xb0c | 172 | #define DMA0_WORD1_CMP_ENABLE 0xb0c |
173 | #define DMA1_WORD1_CMP_ENABLE 0xb1c | 173 | #define DMA1_WORD1_CMP_ENABLE 0xb1c |
174 | #define DMA2_WORD1_CMP_ENABLE 0xb2c | 174 | #define DMA2_WORD1_CMP_ENABLE 0xb2c |
175 | #define DMA3_WORD1_CMP_ENABLE 0xb3c | 175 | #define DMA3_WORD1_CMP_ENABLE 0xb3c |
176 | #define DMA4_WORD1_CMP_ENABLE 0xb4c | 176 | #define DMA4_WORD1_CMP_ENABLE 0xb4c |
177 | #define DMA_WORD1_CMP_ENABLE(chan) (DMA_SREG(DMA0_WORD1_CMP_ENABLE,chan)) | 177 | #define DMA_WORD1_CMP_ENABLE(chan) (DMA_SREG(DMA0_WORD1_CMP_ENABLE, chan)) |
178 | /* word 1 compare enable flags */ | 178 | /* word 1 compare enable flags */ |
179 | #define DMA_WORD1_CMP_MATCH_OTHERBUS (1<<15) | 179 | #define DMA_WORD1_CMP_MATCH_OTHERBUS (1<<15) |
180 | #define DMA_WORD1_CMP_MATCH_BROADCAST (1<<14) | 180 | #define DMA_WORD1_CMP_MATCH_BROADCAST (1<<14) |
@@ -211,7 +211,6 @@ | |||
211 | #define LINK_PHY_WDATA(data) (data<<16) | 211 | #define LINK_PHY_WDATA(data) (data<<16) |
212 | #define LINK_PHY_RADDR(addr) (addr<<8) | 212 | #define LINK_PHY_RADDR(addr) (addr<<8) |
213 | 213 | ||
214 | |||
215 | #define LINK_INT_STATUS 0xf14 | 214 | #define LINK_INT_STATUS 0xf14 |
216 | #define LINK_INT_ENABLE 0xf18 | 215 | #define LINK_INT_ENABLE 0xf18 |
217 | /* status and enable have identical bit numbers */ | 216 | /* status and enable have identical bit numbers */ |
@@ -235,4 +234,4 @@ | |||
235 | #define LINK_INT_GRF_OVER_FLOW (1<<5) | 234 | #define LINK_INT_GRF_OVER_FLOW (1<<5) |
236 | #define LINK_INT_ITF_UNDER_FLOW (1<<4) | 235 | #define LINK_INT_ITF_UNDER_FLOW (1<<4) |
237 | #define LINK_INT_ATF_UNDER_FLOW (1<<3) | 236 | #define LINK_INT_ATF_UNDER_FLOW (1<<3) |
238 | #define LINK_INT_IARB_FAILED (1<<0) | 237 | #define LINK_INT_IARB_FAILED (1<<0) |