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authorStefan Richter <stefanr@s5r6.in-berlin.de>2007-01-21 14:44:09 -0500
committerStefan Richter <stefanr@s5r6.in-berlin.de>2007-03-09 16:02:40 -0500
commit5e20c282184fd5794661b6688883231ff5348abc (patch)
treed9ea9b86d5e2bcc4ef4d8def27102a76ac4b05ef /drivers/firewire/fw-ohci.h
parent95688e97cdf7453cde22eaa73cc2ab6b113c1853 (diff)
firewire: whitespace adjustments
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de> Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Diffstat (limited to 'drivers/firewire/fw-ohci.h')
-rw-r--r--drivers/firewire/fw-ohci.h44
1 files changed, 22 insertions, 22 deletions
diff --git a/drivers/firewire/fw-ohci.h b/drivers/firewire/fw-ohci.h
index 35e2a759e017..a562305078bb 100644
--- a/drivers/firewire/fw-ohci.h
+++ b/drivers/firewire/fw-ohci.h
@@ -63,7 +63,7 @@
63#define OHCI1394_PhyControl_Read(addr) (((addr) << 8) | 0x00008000) 63#define OHCI1394_PhyControl_Read(addr) (((addr) << 8) | 0x00008000)
64#define OHCI1394_PhyControl_ReadDone 0x80000000 64#define OHCI1394_PhyControl_ReadDone 0x80000000
65#define OHCI1394_PhyControl_ReadData(r) (((r) & 0x00ff0000) >> 16) 65#define OHCI1394_PhyControl_ReadData(r) (((r) & 0x00ff0000) >> 16)
66#define OHCI1394_PhyControl_Write(addr, data) (((addr) << 8) | (data) | 0x00004000) 66#define OHCI1394_PhyControl_Write(addr, data) (((addr) << 8) | (data) | 0x00004000)
67#define OHCI1394_PhyControl_WriteDone 0x00004000 67#define OHCI1394_PhyControl_WriteDone 0x00004000
68#define OHCI1394_IsochronousCycleTimer 0x0F0 68#define OHCI1394_IsochronousCycleTimer 0x0F0
69#define OHCI1394_AsReqFilterHiSet 0x100 69#define OHCI1394_AsReqFilterHiSet 0x100
@@ -109,27 +109,27 @@
109#define OHCI1394_IsoRcvContextMatch(n) (0x410 + 32 * (n)) 109#define OHCI1394_IsoRcvContextMatch(n) (0x410 + 32 * (n))
110 110
111/* Interrupts Mask/Events */ 111/* Interrupts Mask/Events */
112#define OHCI1394_reqTxComplete 0x00000001 112#define OHCI1394_reqTxComplete 0x00000001
113#define OHCI1394_respTxComplete 0x00000002 113#define OHCI1394_respTxComplete 0x00000002
114#define OHCI1394_ARRQ 0x00000004 114#define OHCI1394_ARRQ 0x00000004
115#define OHCI1394_ARRS 0x00000008 115#define OHCI1394_ARRS 0x00000008
116#define OHCI1394_RQPkt 0x00000010 116#define OHCI1394_RQPkt 0x00000010
117#define OHCI1394_RSPkt 0x00000020 117#define OHCI1394_RSPkt 0x00000020
118#define OHCI1394_isochTx 0x00000040 118#define OHCI1394_isochTx 0x00000040
119#define OHCI1394_isochRx 0x00000080 119#define OHCI1394_isochRx 0x00000080
120#define OHCI1394_postedWriteErr 0x00000100 120#define OHCI1394_postedWriteErr 0x00000100
121#define OHCI1394_lockRespErr 0x00000200 121#define OHCI1394_lockRespErr 0x00000200
122#define OHCI1394_selfIDComplete 0x00010000 122#define OHCI1394_selfIDComplete 0x00010000
123#define OHCI1394_busReset 0x00020000 123#define OHCI1394_busReset 0x00020000
124#define OHCI1394_phy 0x00080000 124#define OHCI1394_phy 0x00080000
125#define OHCI1394_cycleSynch 0x00100000 125#define OHCI1394_cycleSynch 0x00100000
126#define OHCI1394_cycle64Seconds 0x00200000 126#define OHCI1394_cycle64Seconds 0x00200000
127#define OHCI1394_cycleLost 0x00400000 127#define OHCI1394_cycleLost 0x00400000
128#define OHCI1394_cycleInconsistent 0x00800000 128#define OHCI1394_cycleInconsistent 0x00800000
129#define OHCI1394_unrecoverableError 0x01000000 129#define OHCI1394_unrecoverableError 0x01000000
130#define OHCI1394_cycleTooLong 0x02000000 130#define OHCI1394_cycleTooLong 0x02000000
131#define OHCI1394_phyRegRcvd 0x04000000 131#define OHCI1394_phyRegRcvd 0x04000000
132#define OHCI1394_masterIntEnable 0x80000000 132#define OHCI1394_masterIntEnable 0x80000000
133 133
134#define OHCI1394_evt_no_status 0x0 134#define OHCI1394_evt_no_status 0x0
135#define OHCI1394_evt_long_packet 0x2 135#define OHCI1394_evt_long_packet 0x2