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authorKristian Høgsberg <krh@redhat.com>2007-05-07 20:33:32 -0400
committerStefan Richter <stefanr@s5r6.in-berlin.de>2007-05-10 12:24:13 -0400
commitc781c06d119d04601727f2fbc30151e6760d536d (patch)
tree1faf19acc6bc2a2a3b3bdae8368e395e75cd7518 /drivers/firewire/fw-ohci.c
parente175569c4639872b5cf242c9d4a71cc40c5f3c29 (diff)
firewire: Clean up comment style.
Drop filenames from file preamble, drop editor annotations and use standard indent style for block comments. Signed-off-by: Kristian Hoegsberg <krh@redhat.com> Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de> (fixed typo)
Diffstat (limited to 'drivers/firewire/fw-ohci.c')
-rw-r--r--drivers/firewire/fw-ohci.c144
1 files changed, 94 insertions, 50 deletions
diff --git a/drivers/firewire/fw-ohci.c b/drivers/firewire/fw-ohci.c
index 34eb4681e272..beb924403dab 100644
--- a/drivers/firewire/fw-ohci.c
+++ b/drivers/firewire/fw-ohci.c
@@ -1,6 +1,6 @@
1/* -*- c-basic-offset: 8 -*- 1/*
2 * Driver for OHCI 1394 controllers
2 * 3 *
3 * fw-ohci.c - Driver for OHCI 1394 boards
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
@@ -141,8 +141,10 @@ struct fw_ohci {
141 int request_generation; 141 int request_generation;
142 u32 bus_seconds; 142 u32 bus_seconds;
143 143
144 /* Spinlock for accessing fw_ohci data. Never call out of 144 /*
145 * this driver with this lock held. */ 145 * Spinlock for accessing fw_ohci data. Never call out of
146 * this driver with this lock held.
147 */
146 spinlock_t lock; 148 spinlock_t lock;
147 u32 self_id_buffer[512]; 149 u32 self_id_buffer[512];
148 150
@@ -328,13 +330,15 @@ static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
328 p.timestamp = status & 0xffff; 330 p.timestamp = status & 0xffff;
329 p.generation = ohci->request_generation; 331 p.generation = ohci->request_generation;
330 332
331 /* The OHCI bus reset handler synthesizes a phy packet with 333 /*
334 * The OHCI bus reset handler synthesizes a phy packet with
332 * the new generation number when a bus reset happens (see 335 * the new generation number when a bus reset happens (see
333 * section 8.4.2.3). This helps us determine when a request 336 * section 8.4.2.3). This helps us determine when a request
334 * was received and make sure we send the response in the same 337 * was received and make sure we send the response in the same
335 * generation. We only need this for requests; for responses 338 * generation. We only need this for requests; for responses
336 * we use the unique tlabel for finding the matching 339 * we use the unique tlabel for finding the matching
337 * request. */ 340 * request.
341 */
338 342
339 if (p.ack + 16 == 0x09) 343 if (p.ack + 16 == 0x09)
340 ohci->request_generation = (buffer[2] >> 16) & 0xff; 344 ohci->request_generation = (buffer[2] >> 16) & 0xff;
@@ -360,9 +364,11 @@ static void ar_context_tasklet(unsigned long data)
360 if (d->res_count == 0) { 364 if (d->res_count == 0) {
361 size_t size, rest, offset; 365 size_t size, rest, offset;
362 366
363 /* This descriptor is finished and we may have a 367 /*
368 * This descriptor is finished and we may have a
364 * packet split across this and the next buffer. We 369 * packet split across this and the next buffer. We
365 * reuse the page for reassembling the split packet. */ 370 * reuse the page for reassembling the split packet.
371 */
366 372
367 offset = offsetof(struct ar_buffer, data); 373 offset = offsetof(struct ar_buffer, data);
368 dma_unmap_single(ohci->card.device, 374 dma_unmap_single(ohci->card.device,
@@ -473,11 +479,13 @@ context_init(struct context *ctx, struct fw_ohci *ohci,
473 ctx->tail_descriptor = ctx->buffer; 479 ctx->tail_descriptor = ctx->buffer;
474 ctx->tail_descriptor_last = ctx->buffer; 480 ctx->tail_descriptor_last = ctx->buffer;
475 481
476 /* We put a dummy descriptor in the buffer that has a NULL 482 /*
483 * We put a dummy descriptor in the buffer that has a NULL
477 * branch address and looks like it's been sent. That way we 484 * branch address and looks like it's been sent. That way we
478 * have a descriptor to append DMA programs to. Also, the 485 * have a descriptor to append DMA programs to. Also, the
479 * ring buffer invariant is that it always has at least one 486 * ring buffer invariant is that it always has at least one
480 * element so that head == tail means buffer full. */ 487 * element so that head == tail means buffer full.
488 */
481 489
482 memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor); 490 memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor);
483 ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last); 491 ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last);
@@ -575,9 +583,11 @@ struct driver_data {
575 struct fw_packet *packet; 583 struct fw_packet *packet;
576}; 584};
577 585
578/* This function apppends a packet to the DMA queue for transmission. 586/*
587 * This function apppends a packet to the DMA queue for transmission.
579 * Must always be called with the ochi->lock held to ensure proper 588 * Must always be called with the ochi->lock held to ensure proper
580 * generation handling and locking around packet queue manipulation. */ 589 * generation handling and locking around packet queue manipulation.
590 */
581static int 591static int
582at_context_queue_packet(struct context *ctx, struct fw_packet *packet) 592at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
583{ 593{
@@ -598,10 +608,12 @@ at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
598 d[0].control = cpu_to_le16(descriptor_key_immediate); 608 d[0].control = cpu_to_le16(descriptor_key_immediate);
599 d[0].res_count = cpu_to_le16(packet->timestamp); 609 d[0].res_count = cpu_to_le16(packet->timestamp);
600 610
601 /* The DMA format for asyncronous link packets is different 611 /*
612 * The DMA format for asyncronous link packets is different
602 * from the IEEE1394 layout, so shift the fields around 613 * from the IEEE1394 layout, so shift the fields around
603 * accordingly. If header_length is 8, it's a PHY packet, to 614 * accordingly. If header_length is 8, it's a PHY packet, to
604 * which we need to prepend an extra quadlet. */ 615 * which we need to prepend an extra quadlet.
616 */
605 617
606 header = (__le32 *) &d[1]; 618 header = (__le32 *) &d[1];
607 if (packet->header_length > 8) { 619 if (packet->header_length > 8) {
@@ -703,14 +715,18 @@ static int handle_at_packet(struct context *context,
703 break; 715 break;
704 716
705 case OHCI1394_evt_flushed: 717 case OHCI1394_evt_flushed:
706 /* The packet was flushed should give same error as 718 /*
707 * when we try to use a stale generation count. */ 719 * The packet was flushed should give same error as
720 * when we try to use a stale generation count.
721 */
708 packet->ack = RCODE_GENERATION; 722 packet->ack = RCODE_GENERATION;
709 break; 723 break;
710 724
711 case OHCI1394_evt_missing_ack: 725 case OHCI1394_evt_missing_ack:
712 /* Using a valid (current) generation count, but the 726 /*
713 * node is not on the bus or not sending acks. */ 727 * Using a valid (current) generation count, but the
728 * node is not on the bus or not sending acks.
729 */
714 packet->ack = RCODE_NO_ACK; 730 packet->ack = RCODE_NO_ACK;
715 break; 731 break;
716 732
@@ -887,10 +903,12 @@ static void bus_reset_tasklet(unsigned long data)
887 } 903 }
888 ohci->node_id = reg & 0xffff; 904 ohci->node_id = reg & 0xffff;
889 905
890 /* The count in the SelfIDCount register is the number of 906 /*
907 * The count in the SelfIDCount register is the number of
891 * bytes in the self ID receive buffer. Since we also receive 908 * bytes in the self ID receive buffer. Since we also receive
892 * the inverted quadlets and a header quadlet, we shift one 909 * the inverted quadlets and a header quadlet, we shift one
893 * bit extra to get the actual number of self IDs. */ 910 * bit extra to get the actual number of self IDs.
911 */
894 912
895 self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff; 913 self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
896 generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; 914 generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
@@ -901,7 +919,8 @@ static void bus_reset_tasklet(unsigned long data)
901 ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]); 919 ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
902 } 920 }
903 921
904 /* Check the consistency of the self IDs we just read. The 922 /*
923 * Check the consistency of the self IDs we just read. The
905 * problem we face is that a new bus reset can start while we 924 * problem we face is that a new bus reset can start while we
906 * read out the self IDs from the DMA buffer. If this happens, 925 * read out the self IDs from the DMA buffer. If this happens,
907 * the DMA buffer will be overwritten with new self IDs and we 926 * the DMA buffer will be overwritten with new self IDs and we
@@ -911,7 +930,8 @@ static void bus_reset_tasklet(unsigned long data)
911 * self IDs in the buffer before reading them out and compare 930 * self IDs in the buffer before reading them out and compare
912 * it to the current generation after reading them out. If 931 * it to the current generation after reading them out. If
913 * the two generations match we know we have a consistent set 932 * the two generations match we know we have a consistent set
914 * of self IDs. */ 933 * of self IDs.
934 */
915 935
916 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; 936 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
917 if (new_generation != generation) { 937 if (new_generation != generation) {
@@ -928,12 +948,14 @@ static void bus_reset_tasklet(unsigned long data)
928 context_stop(&ohci->at_response_ctx); 948 context_stop(&ohci->at_response_ctx);
929 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 949 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
930 950
931 /* This next bit is unrelated to the AT context stuff but we 951 /*
952 * This next bit is unrelated to the AT context stuff but we
932 * have to do it under the spinlock also. If a new config rom 953 * have to do it under the spinlock also. If a new config rom
933 * was set up before this reset, the old one is now no longer 954 * was set up before this reset, the old one is now no longer
934 * in use and we can free it. Update the config rom pointers 955 * in use and we can free it. Update the config rom pointers
935 * to point to the current config rom and clear the 956 * to point to the current config rom and clear the
936 * next_config_rom pointer so a new udpate can take place. */ 957 * next_config_rom pointer so a new udpate can take place.
958 */
937 959
938 if (ohci->next_config_rom != NULL) { 960 if (ohci->next_config_rom != NULL) {
939 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 961 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
@@ -942,10 +964,12 @@ static void bus_reset_tasklet(unsigned long data)
942 ohci->config_rom_bus = ohci->next_config_rom_bus; 964 ohci->config_rom_bus = ohci->next_config_rom_bus;
943 ohci->next_config_rom = NULL; 965 ohci->next_config_rom = NULL;
944 966
945 /* Restore config_rom image and manually update 967 /*
968 * Restore config_rom image and manually update
946 * config_rom registers. Writing the header quadlet 969 * config_rom registers. Writing the header quadlet
947 * will indicate that the config rom is ready, so we 970 * will indicate that the config rom is ready, so we
948 * do that last. */ 971 * do that last.
972 */
949 reg_write(ohci, OHCI1394_BusOptions, 973 reg_write(ohci, OHCI1394_BusOptions,
950 be32_to_cpu(ohci->config_rom[2])); 974 be32_to_cpu(ohci->config_rom[2]));
951 ohci->config_rom[0] = cpu_to_be32(ohci->next_header); 975 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
@@ -1018,7 +1042,8 @@ static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1018 struct fw_ohci *ohci = fw_ohci(card); 1042 struct fw_ohci *ohci = fw_ohci(card);
1019 struct pci_dev *dev = to_pci_dev(card->device); 1043 struct pci_dev *dev = to_pci_dev(card->device);
1020 1044
1021 /* When the link is not yet enabled, the atomic config rom 1045 /*
1046 * When the link is not yet enabled, the atomic config rom
1022 * update mechanism described below in ohci_set_config_rom() 1047 * update mechanism described below in ohci_set_config_rom()
1023 * is not active. We have to update ConfigRomHeader and 1048 * is not active. We have to update ConfigRomHeader and
1024 * BusOptions manually, and the write to ConfigROMmap takes 1049 * BusOptions manually, and the write to ConfigROMmap takes
@@ -1067,8 +1092,10 @@ static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1067 OHCI1394_HCControl_BIBimageValid); 1092 OHCI1394_HCControl_BIBimageValid);
1068 flush_writes(ohci); 1093 flush_writes(ohci);
1069 1094
1070 /* We are ready to go, initiate bus reset to finish the 1095 /*
1071 * initialization. */ 1096 * We are ready to go, initiate bus reset to finish the
1097 * initialization.
1098 */
1072 1099
1073 fw_core_initiate_bus_reset(&ohci->card, 1); 1100 fw_core_initiate_bus_reset(&ohci->card, 1);
1074 1101
@@ -1086,7 +1113,8 @@ ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1086 1113
1087 ohci = fw_ohci(card); 1114 ohci = fw_ohci(card);
1088 1115
1089 /* When the OHCI controller is enabled, the config rom update 1116 /*
1117 * When the OHCI controller is enabled, the config rom update
1090 * mechanism is a bit tricky, but easy enough to use. See 1118 * mechanism is a bit tricky, but easy enough to use. See
1091 * section 5.5.6 in the OHCI specification. 1119 * section 5.5.6 in the OHCI specification.
1092 * 1120 *
@@ -1141,11 +1169,13 @@ ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1141 1169
1142 spin_unlock_irqrestore(&ohci->lock, flags); 1170 spin_unlock_irqrestore(&ohci->lock, flags);
1143 1171
1144 /* Now initiate a bus reset to have the changes take 1172 /*
1173 * Now initiate a bus reset to have the changes take
1145 * effect. We clean up the old config rom memory and DMA 1174 * effect. We clean up the old config rom memory and DMA
1146 * mappings in the bus reset tasklet, since the OHCI 1175 * mappings in the bus reset tasklet, since the OHCI
1147 * controller could need to access it before the bus reset 1176 * controller could need to access it before the bus reset
1148 * takes effect. */ 1177 * takes effect.
1178 */
1149 if (retval == 0) 1179 if (retval == 0)
1150 fw_core_initiate_bus_reset(&ohci->card, 1); 1180 fw_core_initiate_bus_reset(&ohci->card, 1);
1151 1181
@@ -1196,8 +1226,10 @@ ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1196 unsigned long flags; 1226 unsigned long flags;
1197 int n, retval = 0; 1227 int n, retval = 0;
1198 1228
1199 /* FIXME: Make sure this bitmask is cleared when we clear the busReset 1229 /*
1200 * interrupt bit. Clear physReqResourceAllBuses on bus reset. */ 1230 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1231 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1232 */
1201 1233
1202 spin_lock_irqsave(&ohci->lock, flags); 1234 spin_lock_irqsave(&ohci->lock, flags);
1203 1235
@@ -1206,8 +1238,10 @@ ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1206 goto out; 1238 goto out;
1207 } 1239 }
1208 1240
1209 /* NOTE, if the node ID contains a non-local bus ID, physical DMA is 1241 /*
1210 * enabled for _all_ nodes on remote buses. */ 1242 * Note, if the node ID contains a non-local bus ID, physical DMA is
1243 * enabled for _all_ nodes on remote buses.
1244 */
1211 1245
1212 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 1246 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1213 if (n < 32) 1247 if (n < 32)
@@ -1257,11 +1291,13 @@ static int handle_ir_dualbuffer_packet(struct context *context,
1257 p = db + 1; 1291 p = db + 1;
1258 end = p + header_length; 1292 end = p + header_length;
1259 while (p < end && i + ctx->base.header_size <= PAGE_SIZE) { 1293 while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1260 /* The iso header is byteswapped to little endian by 1294 /*
1295 * The iso header is byteswapped to little endian by
1261 * the controller, but the remaining header quadlets 1296 * the controller, but the remaining header quadlets
1262 * are big endian. We want to present all the headers 1297 * are big endian. We want to present all the headers
1263 * as big endian, so we have to swap the first 1298 * as big endian, so we have to swap the first
1264 * quadlet. */ 1299 * quadlet.
1300 */
1265 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); 1301 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1266 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4); 1302 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1267 i += ctx->base.header_size; 1303 i += ctx->base.header_size;
@@ -1457,8 +1493,10 @@ ohci_queue_iso_transmit(struct fw_iso_context *base,
1457 u32 payload_index, payload_end_index, next_page_index; 1493 u32 payload_index, payload_end_index, next_page_index;
1458 int page, end_page, i, length, offset; 1494 int page, end_page, i, length, offset;
1459 1495
1460 /* FIXME: Cycle lost behavior should be configurable: lose 1496 /*
1461 * packet, retransmit or terminate.. */ 1497 * FIXME: Cycle lost behavior should be configurable: lose
1498 * packet, retransmit or terminate..
1499 */
1462 1500
1463 p = packet; 1501 p = packet;
1464 payload_index = payload; 1502 payload_index = payload;
@@ -1553,8 +1591,10 @@ ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
1553 u32 z, header_z, length, rest; 1591 u32 z, header_z, length, rest;
1554 int page, offset, packet_count, header_size; 1592 int page, offset, packet_count, header_size;
1555 1593
1556 /* FIXME: Cycle lost behavior should be configurable: lose 1594 /*
1557 * packet, retransmit or terminate.. */ 1595 * FIXME: Cycle lost behavior should be configurable: lose
1596 * packet, retransmit or terminate..
1597 */
1558 1598
1559 if (packet->skip) { 1599 if (packet->skip) {
1560 d = context_get_descriptors(&ctx->context, 2, &d_bus); 1600 d = context_get_descriptors(&ctx->context, 2, &d_bus);
@@ -1572,8 +1612,10 @@ ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
1572 p = packet; 1612 p = packet;
1573 z = 2; 1613 z = 2;
1574 1614
1575 /* The OHCI controller puts the status word in the header 1615 /*
1576 * buffer too, so we need 4 extra bytes per packet. */ 1616 * The OHCI controller puts the status word in the header
1617 * buffer too, so we need 4 extra bytes per packet.
1618 */
1577 packet_count = p->header_length / ctx->base.header_size; 1619 packet_count = p->header_length / ctx->base.header_size;
1578 header_size = packet_count * (ctx->base.header_size + 4); 1620 header_size = packet_count * (ctx->base.header_size + 4);
1579 1621
@@ -1673,8 +1715,6 @@ static int software_reset(struct fw_ohci *ohci)
1673 return -EBUSY; 1715 return -EBUSY;
1674} 1716}
1675 1717
1676/* ---------- pci subsystem interface ---------- */
1677
1678enum { 1718enum {
1679 CLEANUP_SELF_ID, 1719 CLEANUP_SELF_ID,
1680 CLEANUP_REGISTERS, 1720 CLEANUP_REGISTERS,
@@ -1753,11 +1793,13 @@ pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1753 return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY); 1793 return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY);
1754 } 1794 }
1755 1795
1756 /* Now enable LPS, which we need in order to start accessing 1796 /*
1797 * Now enable LPS, which we need in order to start accessing
1757 * most of the registers. In fact, on some cards (ALI M5251), 1798 * most of the registers. In fact, on some cards (ALI M5251),
1758 * accessing registers in the SClk domain without LPS enabled 1799 * accessing registers in the SClk domain without LPS enabled
1759 * will lock up the machine. Wait 50msec to make sure we have 1800 * will lock up the machine. Wait 50msec to make sure we have
1760 * full link enabled. */ 1801 * full link enabled.
1802 */
1761 reg_write(ohci, OHCI1394_HCControlSet, 1803 reg_write(ohci, OHCI1394_HCControlSet,
1762 OHCI1394_HCControl_LPS | 1804 OHCI1394_HCControl_LPS |
1763 OHCI1394_HCControl_postedWriteEnable); 1805 OHCI1394_HCControl_postedWriteEnable);
@@ -1854,8 +1896,10 @@ static void pci_remove(struct pci_dev *dev)
1854 flush_writes(ohci); 1896 flush_writes(ohci);
1855 fw_core_remove_card(&ohci->card); 1897 fw_core_remove_card(&ohci->card);
1856 1898
1857 /* FIXME: Fail all pending packets here, now that the upper 1899 /*
1858 * layers can't queue any more. */ 1900 * FIXME: Fail all pending packets here, now that the upper
1901 * layers can't queue any more.
1902 */
1859 1903
1860 software_reset(ohci); 1904 software_reset(ohci);
1861 free_irq(dev->irq, ohci); 1905 free_irq(dev->irq, ohci);