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authorClemens Ladisch <clemens@ladisch.de>2010-06-10 02:36:37 -0400
committerClemens Ladisch <clemens@ladisch.de>2010-06-10 02:36:37 -0400
commit4ffb7a6a066e4be4577976d1c08e237c7479770a (patch)
treefd4c275e8ef894d60602e1b4d1f81150e54b32f8 /drivers/firewire/core-transaction.c
parent3d1f46eb60b155c705e389ecdf313f11b4b91976 (diff)
firewire: add CSR cmstr support
Implement the cmstr bit, which is required for cycle master capable nodes and tested for by the Base 1394 Test Suite. This bit allows the bus master to disable cycle start packets; there are bus master implementations that actually do this. Signed-off-by: Clemens Ladisch <clemens@ladisch.de>
Diffstat (limited to 'drivers/firewire/core-transaction.c')
-rw-r--r--drivers/firewire/core-transaction.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/firewire/core-transaction.c b/drivers/firewire/core-transaction.c
index dd8ef650a7cb..e0c6cce894cf 100644
--- a/drivers/firewire/core-transaction.c
+++ b/drivers/firewire/core-transaction.c
@@ -1003,7 +1003,12 @@ static u32 read_state_register(struct fw_card *card)
1003 * reset, but then cleared when the units are ready again, which 1003 * reset, but then cleared when the units are ready again, which
1004 * happens immediately for us. 1004 * happens immediately for us.
1005 */ 1005 */
1006 return 0; 1006 u32 value = 0x0000;
1007
1008 /* Bit 8 (cmstr): */
1009 value |= card->driver->read_csr_reg(card, CSR_STATE_CLEAR);
1010
1011 return value;
1007} 1012}
1008 1013
1009static void update_split_timeout(struct fw_card *card) 1014static void update_split_timeout(struct fw_card *card)
@@ -1034,6 +1039,8 @@ static void handle_registers(struct fw_card *card, struct fw_request *request,
1034 if (tcode == TCODE_READ_QUADLET_REQUEST) { 1039 if (tcode == TCODE_READ_QUADLET_REQUEST) {
1035 *data = cpu_to_be32(read_state_register(card)); 1040 *data = cpu_to_be32(read_state_register(card));
1036 } else if (tcode == TCODE_WRITE_QUADLET_REQUEST) { 1041 } else if (tcode == TCODE_WRITE_QUADLET_REQUEST) {
1042 card->driver->write_csr_reg(card, CSR_STATE_CLEAR,
1043 be32_to_cpu(*data));
1037 } else { 1044 } else {
1038 rcode = RCODE_TYPE_ERROR; 1045 rcode = RCODE_TYPE_ERROR;
1039 } 1046 }
@@ -1043,7 +1050,8 @@ static void handle_registers(struct fw_card *card, struct fw_request *request,
1043 if (tcode == TCODE_READ_QUADLET_REQUEST) { 1050 if (tcode == TCODE_READ_QUADLET_REQUEST) {
1044 *data = cpu_to_be32(read_state_register(card)); 1051 *data = cpu_to_be32(read_state_register(card));
1045 } else if (tcode == TCODE_WRITE_QUADLET_REQUEST) { 1052 } else if (tcode == TCODE_WRITE_QUADLET_REQUEST) {
1046 /* FIXME: implement cmstr */ 1053 card->driver->write_csr_reg(card, CSR_STATE_SET,
1054 be32_to_cpu(*data));
1047 /* FIXME: implement abdicate */ 1055 /* FIXME: implement abdicate */
1048 } else { 1056 } else {
1049 rcode = RCODE_TYPE_ERROR; 1057 rcode = RCODE_TYPE_ERROR;