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authorBorislav Petkov <borislav.petkov@amd.com>2009-11-03 10:18:33 -0500
committerBorislav Petkov <borislav.petkov@amd.com>2009-12-07 13:14:28 -0500
commit68798e176012750fe8487bcfa0aa66fee21eae3c (patch)
tree27ced0aa0f50d1b342b2a18cd430e16385d679c6 /drivers/edac
parent6ba5dcdc44624677bba0bef1dcb93a524f88f8c1 (diff)
amd64_edac: cleanup DRAM cfg low debug output
Carve out the register-specific debug statements into a separate function, clarify meanings of the single bitfields in the register, remove irrelevant output and macros. There should be no functionality change resulting from this patch. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/amd64_edac.c65
-rw-r--r--drivers/edac/amd64_edac.h2
2 files changed, 32 insertions, 35 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 3e5ece6e7c95..cdda8d469cad 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -825,31 +825,42 @@ static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt)
825static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt, 825static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt,
826 int ganged); 826 int ganged);
827 827
828static void amd64_dump_dramcfg_low(u32 dclr, int chan)
829{
830 debugf1("F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);
831
832 debugf1(" DIMM type: %sbuffered; all DIMMs support ECC: %s\n",
833 (dclr & BIT(16)) ? "un" : "",
834 (dclr & BIT(19)) ? "yes" : "no");
835
836 debugf1(" PAR/ERR parity: %s\n",
837 (dclr & BIT(8)) ? "enabled" : "disabled");
838
839 debugf1(" DCT 128bit mode width: %s\n",
840 (dclr & BIT(11)) ? "128b" : "64b");
841
842 debugf1(" x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
843 (dclr & BIT(12)) ? "yes" : "no",
844 (dclr & BIT(13)) ? "yes" : "no",
845 (dclr & BIT(14)) ? "yes" : "no",
846 (dclr & BIT(15)) ? "yes" : "no");
847}
848
828/* Display and decode various NB registers for debug purposes. */ 849/* Display and decode various NB registers for debug purposes. */
829static void amd64_dump_misc_regs(struct amd64_pvt *pvt) 850static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
830{ 851{
831 int ganged; 852 int ganged;
832 853
833 debugf1(" nbcap:0x%8.08x DctDualCap=%s DualNode=%s 8-Node=%s\n", 854 debugf1("F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
834 pvt->nbcap, 855
835 (pvt->nbcap & K8_NBCAP_DCT_DUAL) ? "True" : "False", 856 debugf1(" NB two channel DRAM capable: %s\n",
836 (pvt->nbcap & K8_NBCAP_DUAL_NODE) ? "True" : "False", 857 (pvt->nbcap & K8_NBCAP_DCT_DUAL) ? "yes" : "no");
837 (pvt->nbcap & K8_NBCAP_8_NODE) ? "True" : "False"); 858
838 debugf1(" ECC Capable=%s ChipKill Capable=%s\n", 859 debugf1(" ECC capable: %s, ChipKill ECC capable: %s\n",
839 (pvt->nbcap & K8_NBCAP_SECDED) ? "True" : "False", 860 (pvt->nbcap & K8_NBCAP_SECDED) ? "yes" : "no",
840 (pvt->nbcap & K8_NBCAP_CHIPKILL) ? "True" : "False"); 861 (pvt->nbcap & K8_NBCAP_CHIPKILL) ? "yes" : "no");
841 debugf1(" DramCfg0-low=0x%08x DIMM-ECC=%s Parity=%s Width=%s\n",
842 pvt->dclr0,
843 (pvt->dclr0 & BIT(19)) ? "Enabled" : "Disabled",
844 (pvt->dclr0 & BIT(8)) ? "Enabled" : "Disabled",
845 (pvt->dclr0 & BIT(11)) ? "128b" : "64b");
846 debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s DIMM Type=%s\n",
847 (pvt->dclr0 & BIT(12)) ? "Y" : "N",
848 (pvt->dclr0 & BIT(13)) ? "Y" : "N",
849 (pvt->dclr0 & BIT(14)) ? "Y" : "N",
850 (pvt->dclr0 & BIT(15)) ? "Y" : "N",
851 (pvt->dclr0 & BIT(16)) ? "UN-Buffered" : "Buffered");
852 862
863 amd64_dump_dramcfg_low(pvt->dclr0, 0);
853 864
854 debugf1(" online-spare: 0x%8.08x\n", pvt->online_spare); 865 debugf1(" online-spare: 0x%8.08x\n", pvt->online_spare);
855 866
@@ -877,20 +888,8 @@ static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
877 } 888 }
878 889
879 /* Only if NOT ganged does dcl1 have valid info */ 890 /* Only if NOT ganged does dcl1 have valid info */
880 if (!dct_ganging_enabled(pvt)) { 891 if (!dct_ganging_enabled(pvt))
881 debugf1(" DramCfg1-low=0x%08x DIMM-ECC=%s Parity=%s " 892 amd64_dump_dramcfg_low(pvt->dclr1, 1);
882 "Width=%s\n", pvt->dclr1,
883 (pvt->dclr1 & BIT(19)) ? "Enabled" : "Disabled",
884 (pvt->dclr1 & BIT(8)) ? "Enabled" : "Disabled",
885 (pvt->dclr1 & BIT(11)) ? "128b" : "64b");
886 debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s "
887 "DIMM Type=%s\n",
888 (pvt->dclr1 & BIT(12)) ? "Y" : "N",
889 (pvt->dclr1 & BIT(13)) ? "Y" : "N",
890 (pvt->dclr1 & BIT(14)) ? "Y" : "N",
891 (pvt->dclr1 & BIT(15)) ? "Y" : "N",
892 (pvt->dclr1 & BIT(16)) ? "UN-Buffered" : "Buffered");
893 }
894 893
895 /* 894 /*
896 * Determine if ganged and then dump memory sizes for first controller, 895 * Determine if ganged and then dump memory sizes for first controller,
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 16f2df449a09..24e280423de0 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -384,8 +384,6 @@ enum {
384#define K8_NBCAP_CORES (BIT(12)|BIT(13)) 384#define K8_NBCAP_CORES (BIT(12)|BIT(13))
385#define K8_NBCAP_CHIPKILL BIT(4) 385#define K8_NBCAP_CHIPKILL BIT(4)
386#define K8_NBCAP_SECDED BIT(3) 386#define K8_NBCAP_SECDED BIT(3)
387#define K8_NBCAP_8_NODE BIT(2)
388#define K8_NBCAP_DUAL_NODE BIT(1)
389#define K8_NBCAP_DCT_DUAL BIT(0) 387#define K8_NBCAP_DCT_DUAL BIT(0)
390 388
391/* MSRs */ 389/* MSRs */