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authorMauro Carvalho Chehab <mchehab@redhat.com>2012-04-16 14:10:05 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-05-28 18:13:41 -0400
commit70e2a8379b6e704b2e8cdfcf151954171c36e779 (patch)
tree6473124042e67e6cb21968d7cba4b8fdf7df8bc2 /drivers/edac
parent296da591ea1d81b8d94d6e79b6c235bb820526b9 (diff)
i7300_edac: convert driver to use the new edac ABI
The legacy edac ABI is going to be removed. Port the driver to use and benefit from the new API functionality. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/i7300_edac.c78
1 files changed, 30 insertions, 48 deletions
diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c
index d6f3a2d0f70a..c2cf9771692a 100644
--- a/drivers/edac/i7300_edac.c
+++ b/drivers/edac/i7300_edac.c
@@ -464,17 +464,14 @@ static void i7300_process_fbd_error(struct mem_ctl_info *mci)
464 FERR_FAT_FBD, error_reg); 464 FERR_FAT_FBD, error_reg);
465 465
466 snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, 466 snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
467 "FATAL (Branch=%d DRAM-Bank=%d %s " 467 "Bank=%d RAS=%d CAS=%d Err=0x%lx (%s))",
468 "RAS=%d CAS=%d Err=0x%lx (%s))", 468 bank, ras, cas, errors, specific);
469 branch, bank, 469
470 is_wr ? "RDWR" : "RD", 470 edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 0, 0, 0,
471 ras, cas, 471 branch, -1, rank,
472 errors, specific); 472 is_wr ? "Write error" : "Read error",
473 473 pvt->tmp_prt_buffer, NULL);
474 /* Call the helper to output message */ 474
475 edac_mc_handle_fbd_ue(mci, rank, branch << 1,
476 (branch << 1) + 1,
477 pvt->tmp_prt_buffer);
478 } 475 }
479 476
480 /* read in the 1st NON-FATAL error register */ 477 /* read in the 1st NON-FATAL error register */
@@ -513,23 +510,14 @@ static void i7300_process_fbd_error(struct mem_ctl_info *mci)
513 510
514 /* Form out message */ 511 /* Form out message */
515 snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, 512 snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
516 "Corrected error (Branch=%d, Channel %d), " 513 "DRAM-Bank=%d RAS=%d CAS=%d, Err=0x%lx (%s))",
517 " DRAM-Bank=%d %s " 514 bank, ras, cas, errors, specific);
518 "RAS=%d CAS=%d, CE Err=0x%lx, Syndrome=0x%08x(%s))", 515
519 branch, channel, 516 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0,
520 bank, 517 syndrome,
521 is_wr ? "RDWR" : "RD", 518 branch >> 1, channel % 2, rank,
522 ras, cas, 519 is_wr ? "Write error" : "Read error",
523 errors, syndrome, specific); 520 pvt->tmp_prt_buffer, NULL);
524
525 /*
526 * Call the helper to output message
527 * NOTE: Errors are reported per-branch, and not per-channel
528 * Currently, we don't know how to identify the right
529 * channel.
530 */
531 edac_mc_handle_fbd_ce(mci, rank, channel,
532 pvt->tmp_prt_buffer);
533 } 521 }
534 return; 522 return;
535} 523}
@@ -807,9 +795,10 @@ static int i7300_init_csrows(struct mem_ctl_info *mci)
807 for (ch = 0; ch < MAX_CH_PER_BRANCH; ch++) { 795 for (ch = 0; ch < MAX_CH_PER_BRANCH; ch++) {
808 int channel = to_channel(ch, branch); 796 int channel = to_channel(ch, branch);
809 797
810 dinfo = &pvt->dimm_info[slot][channel]; 798 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
799 mci->n_layers, branch, ch, slot);
811 800
812 dimm = mci->csrows[slot].channels[branch * MAX_CH_PER_BRANCH + ch].dimm; 801 dinfo = &pvt->dimm_info[slot][channel];
813 802
814 mtr = decode_mtr(pvt, slot, ch, branch, 803 mtr = decode_mtr(pvt, slot, ch, branch,
815 dinfo, dimm); 804 dinfo, dimm);
@@ -1034,10 +1023,8 @@ static int __devinit i7300_init_one(struct pci_dev *pdev,
1034 const struct pci_device_id *id) 1023 const struct pci_device_id *id)
1035{ 1024{
1036 struct mem_ctl_info *mci; 1025 struct mem_ctl_info *mci;
1026 struct edac_mc_layer layers[3];
1037 struct i7300_pvt *pvt; 1027 struct i7300_pvt *pvt;
1038 int num_channels;
1039 int num_dimms_per_channel;
1040 int num_csrows;
1041 int rc; 1028 int rc;
1042 1029
1043 /* wake up device */ 1030 /* wake up device */
@@ -1054,22 +1041,17 @@ static int __devinit i7300_init_one(struct pci_dev *pdev,
1054 if (PCI_FUNC(pdev->devfn) != 0) 1041 if (PCI_FUNC(pdev->devfn) != 0)
1055 return -ENODEV; 1042 return -ENODEV;
1056 1043
1057 /* As we don't have a motherboard identification routine to determine
1058 * actual number of slots/dimms per channel, we thus utilize the
1059 * resource as specified by the chipset. Thus, we might have
1060 * have more DIMMs per channel than actually on the mobo, but this
1061 * allows the driver to support up to the chipset max, without
1062 * some fancy mobo determination.
1063 */
1064 num_dimms_per_channel = MAX_SLOTS;
1065 num_channels = MAX_CHANNELS;
1066 num_csrows = MAX_SLOTS * MAX_CHANNELS;
1067
1068 debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
1069 __func__, num_channels, num_dimms_per_channel, num_csrows);
1070
1071 /* allocate a new MC control structure */ 1044 /* allocate a new MC control structure */
1072 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0); 1045 layers[0].type = EDAC_MC_LAYER_BRANCH;
1046 layers[0].size = MAX_BRANCHES;
1047 layers[0].is_virt_csrow = false;
1048 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1049 layers[1].size = MAX_CH_PER_BRANCH;
1050 layers[1].is_virt_csrow = true;
1051 layers[2].type = EDAC_MC_LAYER_SLOT;
1052 layers[2].size = MAX_SLOTS;
1053 layers[2].is_virt_csrow = true;
1054 mci = new_edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
1073 1055
1074 if (mci == NULL) 1056 if (mci == NULL)
1075 return -ENOMEM; 1057 return -ENOMEM;