diff options
author | Borislav Petkov <borislav.petkov@amd.com> | 2010-12-22 13:48:20 -0500 |
---|---|---|
committer | Borislav Petkov <borislav.petkov@amd.com> | 2011-03-17 09:46:15 -0400 |
commit | c9f4f26eae096c39547139666e8af607c2447f94 (patch) | |
tree | 754fabb84aea79bac1d8a05e3017d4df52ac817b /drivers/edac | |
parent | 78da121e1560805a0e6e11952de30b416accef62 (diff) |
amd64_edac: Cleanup NBCTL code
Remove family names from macro names, drop single bit defines and
comment their meaning instead.
No functional change.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r-- | drivers/edac/amd64_edac.c | 14 | ||||
-rw-r--r-- | drivers/edac/amd64_edac.h | 8 |
2 files changed, 8 insertions, 14 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 495b4d506671..9a8a31317071 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c | |||
@@ -2196,21 +2196,20 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid, | |||
2196 | struct pci_dev *F3) | 2196 | struct pci_dev *F3) |
2197 | { | 2197 | { |
2198 | bool ret = true; | 2198 | bool ret = true; |
2199 | u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn; | 2199 | u32 value, mask = 0x3; /* UECC/CECC enable */ |
2200 | 2200 | ||
2201 | if (toggle_ecc_err_reporting(s, nid, ON)) { | 2201 | if (toggle_ecc_err_reporting(s, nid, ON)) { |
2202 | amd64_warn("Error enabling ECC reporting over MCGCTL!\n"); | 2202 | amd64_warn("Error enabling ECC reporting over MCGCTL!\n"); |
2203 | return false; | 2203 | return false; |
2204 | } | 2204 | } |
2205 | 2205 | ||
2206 | amd64_read_pci_cfg(F3, K8_NBCTL, &value); | 2206 | amd64_read_pci_cfg(F3, NBCTL, &value); |
2207 | 2207 | ||
2208 | /* turn on UECCEn and CECCEn bits */ | ||
2209 | s->old_nbctl = value & mask; | 2208 | s->old_nbctl = value & mask; |
2210 | s->nbctl_valid = true; | 2209 | s->nbctl_valid = true; |
2211 | 2210 | ||
2212 | value |= mask; | 2211 | value |= mask; |
2213 | amd64_write_pci_cfg(F3, K8_NBCTL, value); | 2212 | amd64_write_pci_cfg(F3, NBCTL, value); |
2214 | 2213 | ||
2215 | amd64_read_pci_cfg(F3, K8_NBCFG, &value); | 2214 | amd64_read_pci_cfg(F3, K8_NBCFG, &value); |
2216 | 2215 | ||
@@ -2250,16 +2249,17 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid, | |||
2250 | static void restore_ecc_error_reporting(struct ecc_settings *s, u8 nid, | 2249 | static void restore_ecc_error_reporting(struct ecc_settings *s, u8 nid, |
2251 | struct pci_dev *F3) | 2250 | struct pci_dev *F3) |
2252 | { | 2251 | { |
2253 | u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn; | 2252 | u32 value, mask = 0x3; /* UECC/CECC enable */ |
2253 | |||
2254 | 2254 | ||
2255 | if (!s->nbctl_valid) | 2255 | if (!s->nbctl_valid) |
2256 | return; | 2256 | return; |
2257 | 2257 | ||
2258 | amd64_read_pci_cfg(F3, K8_NBCTL, &value); | 2258 | amd64_read_pci_cfg(F3, NBCTL, &value); |
2259 | value &= ~mask; | 2259 | value &= ~mask; |
2260 | value |= s->old_nbctl; | 2260 | value |= s->old_nbctl; |
2261 | 2261 | ||
2262 | amd64_write_pci_cfg(F3, K8_NBCTL, value); | 2262 | amd64_write_pci_cfg(F3, NBCTL, value); |
2263 | 2263 | ||
2264 | /* restore previous BIOS DRAM ECC "off" setting we force-enabled */ | 2264 | /* restore previous BIOS DRAM ECC "off" setting we force-enabled */ |
2265 | if (!s->flags.nb_ecc_prev) { | 2265 | if (!s->flags.nb_ecc_prev) { |
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 0244c612b3f2..fc609d1164a8 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h | |||
@@ -244,13 +244,7 @@ | |||
244 | /* | 244 | /* |
245 | * Function 3 - Misc Control | 245 | * Function 3 - Misc Control |
246 | */ | 246 | */ |
247 | #define K8_NBCTL 0x40 | 247 | #define NBCTL 0x40 |
248 | |||
249 | /* Correctable ECC error reporting enable */ | ||
250 | #define K8_NBCTL_CECCEn BIT(0) | ||
251 | |||
252 | /* UnCorrectable ECC error reporting enable */ | ||
253 | #define K8_NBCTL_UECCEn BIT(1) | ||
254 | 248 | ||
255 | #define K8_NBCFG 0x44 | 249 | #define K8_NBCFG 0x44 |
256 | #define K8_NBCFG_CHIPKILL BIT(23) | 250 | #define K8_NBCFG_CHIPKILL BIT(23) |