diff options
author | Mauro Carvalho Chehab <mchehab@redhat.com> | 2010-08-26 18:54:51 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2010-08-30 13:56:44 -0400 |
commit | c3af2eaf7a3257f7b44165ec487215574c47fd32 (patch) | |
tree | e27182bd6b713c10a889180086c8eb40a7f63302 /drivers/edac | |
parent | af3d8831e7e2036cd453c852d206b892b19c8820 (diff) |
i7300_edac: add global error registers
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r-- | drivers/edac/i7300_edac.c | 174 |
1 files changed, 92 insertions, 82 deletions
diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c index db194b6b3e42..7e035b6d0d0f 100644 --- a/drivers/edac/i7300_edac.c +++ b/drivers/edac/i7300_edac.c | |||
@@ -50,7 +50,7 @@ | |||
50 | * Except on Single Channel mode of operation | 50 | * Except on Single Channel mode of operation |
51 | * just slot 0/channel0 filled on this mode | 51 | * just slot 0/channel0 filled on this mode |
52 | * On normal operation mode, the two channels on a branch should be | 52 | * On normal operation mode, the two channels on a branch should be |
53 | filled together for the same SLOT# | 53 | * filled together for the same SLOT# |
54 | * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four | 54 | * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four |
55 | * channels on both branches should be filled | 55 | * channels on both branches should be filled |
56 | */ | 56 | */ |
@@ -67,18 +67,24 @@ | |||
67 | #define to_csrow(slot, ch, branch) \ | 67 | #define to_csrow(slot, ch, branch) \ |
68 | (to_channel(ch, branch) | ((slot) << 2)) | 68 | (to_channel(ch, branch) | ((slot) << 2)) |
69 | 69 | ||
70 | 70 | /* | |
71 | /* Device 16, | 71 | * I7300 devices |
72 | * Function 0: System Address (not documented) | ||
73 | * Function 1: Memory Branch Map, Control, Errors Register | ||
74 | * Function 2: FSB Error Registers | ||
75 | * | ||
76 | * All 3 functions of Device 16 (0,1,2) share the SAME DID and | 72 | * All 3 functions of Device 16 (0,1,2) share the SAME DID and |
77 | * uses PCI_DEVICE_ID_INTEL_I7300_MCH_ERR for device 16 (0,1,2), | 73 | * uses PCI_DEVICE_ID_INTEL_I7300_MCH_ERR for device 16 (0,1,2), |
78 | * PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 and PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 | 74 | * PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 and PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 |
79 | * for device 21 (0,1). | 75 | * for device 21 (0,1). |
80 | */ | 76 | */ |
81 | 77 | ||
78 | /**************************************************** | ||
79 | * i7300 Register definitions for memory enumberation | ||
80 | ****************************************************/ | ||
81 | |||
82 | /* | ||
83 | * Device 16, | ||
84 | * Function 0: System Address (not documented) | ||
85 | * Function 1: Memory Branch Map, Control, Errors Register | ||
86 | */ | ||
87 | |||
82 | /* OFFSETS for Function 0 */ | 88 | /* OFFSETS for Function 0 */ |
83 | #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */ | 89 | #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */ |
84 | #define MAXCH 0x56 /* Max Channel Number */ | 90 | #define MAXCH 0x56 /* Max Channel Number */ |
@@ -94,50 +100,6 @@ | |||
94 | #define MIR1 0x84 | 100 | #define MIR1 0x84 |
95 | #define MIR2 0x88 | 101 | #define MIR2 0x88 |
96 | 102 | ||
97 | #if 0 | ||
98 | #define AMIR0 0x8c | ||
99 | #define AMIR1 0x90 | ||
100 | #define AMIR2 0x94 | ||
101 | |||
102 | /*TODO: double check it */ | ||
103 | #define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3fe00) /* bits [17:9] indicate ODD, [8:0] indicate EVEN */ | ||
104 | |||
105 | /* Fatal error registers */ | ||
106 | #define FERR_FAT_FBD 0x98 | ||
107 | |||
108 | /*TODO: double check it */ | ||
109 | #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */ | ||
110 | |||
111 | #define NERR_FAT_FBD 0x9c | ||
112 | #define FERR_NF_FBD 0xa0 | ||
113 | |||
114 | /* Non-fatal error register */ | ||
115 | #define NERR_NF_FBD 0xa4 | ||
116 | |||
117 | /* Enable error mask */ | ||
118 | #define EMASK_FBD 0xa8 | ||
119 | |||
120 | #define ERR0_FBD 0xac | ||
121 | #define ERR1_FBD 0xb0 | ||
122 | #define ERR2_FBD 0xb4 | ||
123 | #define MCERR_FBD 0xb8 | ||
124 | |||
125 | #endif | ||
126 | |||
127 | /* TODO: Dev 16 fn1 allows memory error injection - offsets 0x100-0x10b */ | ||
128 | |||
129 | /* TODO: OFFSETS for Device 16 Function 2 */ | ||
130 | |||
131 | /* | ||
132 | * Device 21, | ||
133 | * Function 0: Memory Map Branch 0 | ||
134 | * | ||
135 | * Device 22, | ||
136 | * Function 0: Memory Map Branch 1 | ||
137 | */ | ||
138 | |||
139 | /* OFFSETS for Function 0 */ | ||
140 | |||
141 | /* | 103 | /* |
142 | * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available | 104 | * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available |
143 | * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it | 105 | * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it |
@@ -171,37 +133,6 @@ const static u16 mtr_regs [MAX_SLOTS] = { | |||
171 | #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) | 133 | #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) |
172 | #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) | 134 | #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) |
173 | 135 | ||
174 | #if 0 | ||
175 | /* OFFSETS for Function 1 */ | ||
176 | |||
177 | /* TODO */ | ||
178 | #define NRECFGLOG 0x74 | ||
179 | #define RECFGLOG 0x78 | ||
180 | #define NRECMEMA 0xbe | ||
181 | #define NRECMEMB 0xc0 | ||
182 | #define NRECFB_DIMMA 0xc4 | ||
183 | #define NRECFB_DIMMB 0xc8 | ||
184 | #define NRECFB_DIMMC 0xcc | ||
185 | #define NRECFB_DIMMD 0xd0 | ||
186 | #define NRECFB_DIMME 0xd4 | ||
187 | #define NRECFB_DIMMF 0xd8 | ||
188 | #define REDMEMA 0xdC | ||
189 | #define RECMEMA 0xf0 | ||
190 | #define RECMEMB 0xf4 | ||
191 | #define RECFB_DIMMA 0xf8 | ||
192 | #define RECFB_DIMMB 0xec | ||
193 | #define RECFB_DIMMC 0xf0 | ||
194 | #define RECFB_DIMMD 0xf4 | ||
195 | #define RECFB_DIMME 0xf8 | ||
196 | #define RECFB_DIMMF 0xfC | ||
197 | |||
198 | /* This applies to FERR_NF_FB-DIMM as well as FERR_FAT_FB-DIMM */ | ||
199 | static inline int extract_fbdchan_indx(u32 x) | ||
200 | { | ||
201 | return (x>>28) & 0x3; | ||
202 | } | ||
203 | #endif | ||
204 | |||
205 | #ifdef CONFIG_EDAC_DEBUG | 136 | #ifdef CONFIG_EDAC_DEBUG |
206 | /* MTR NUMROW */ | 137 | /* MTR NUMROW */ |
207 | static const char *numrow_toString[] = { | 138 | static const char *numrow_toString[] = { |
@@ -220,6 +151,85 @@ static const char *numcol_toString[] = { | |||
220 | }; | 151 | }; |
221 | #endif | 152 | #endif |
222 | 153 | ||
154 | /************************************************ | ||
155 | * i7300 Register definitions for error detection | ||
156 | ************************************************/ | ||
157 | /* | ||
158 | * Device 16.2: Global Error Registers | ||
159 | */ | ||
160 | |||
161 | #define FERR_GLOBAL_LO 0x40 | ||
162 | static const char *ferr_global_name[] = { | ||
163 | [31] = "Internal MCH Fatal Error", | ||
164 | [30] = "Intel QuickData Technology Device Fatal Error", | ||
165 | [29] = "FSB1 Fatal Error", | ||
166 | [28] = "FSB0 Fatal Error", | ||
167 | [27] = "FBD Channel 3 Fatal Error", | ||
168 | [26] = "FBD Channel 2 Fatal Error", | ||
169 | [25] = "FBD Channel 1 Fatal Error", | ||
170 | [24] = "FBD Channel 0 Fatal Error", | ||
171 | [23] = "PCI Express Device 7Fatal Error", | ||
172 | [22] = "PCI Express Device 6 Fatal Error", | ||
173 | [21] = "PCI Express Device 5 Fatal Error", | ||
174 | [20] = "PCI Express Device 4 Fatal Error", | ||
175 | [19] = "PCI Express Device 3 Fatal Error", | ||
176 | [18] = "PCI Express Device 2 Fatal Error", | ||
177 | [17] = "PCI Express Device 1 Fatal Error", | ||
178 | [16] = "ESI Fatal Error", | ||
179 | [15] = "Internal MCH Non-Fatal Error", | ||
180 | [14] = "Intel QuickData Technology Device Non Fatal Error", | ||
181 | [13] = "FSB1 Non-Fatal Error", | ||
182 | [12] = "FSB 0 Non-Fatal Error", | ||
183 | [11] = "FBD Channel 3 Non-Fatal Error", | ||
184 | [10] = "FBD Channel 2 Non-Fatal Error", | ||
185 | [9] = "FBD Channel 1 Non-Fatal Error", | ||
186 | [8] = "FBD Channel 0 Non-Fatal Error", | ||
187 | [7] = "PCI Express Device 7 Non-Fatal Error", | ||
188 | [6] = "PCI Express Device 6 Non-Fatal Error", | ||
189 | [5] = "PCI Express Device 5 Non-Fatal Error", | ||
190 | [4] = "PCI Express Device 4 Non-Fatal Error", | ||
191 | [3] = "PCI Express Device 3 Non-Fatal Error", | ||
192 | [2] = "PCI Express Device 2 Non-Fatal Error", | ||
193 | [1] = "PCI Express Device 1 Non-Fatal Error", | ||
194 | [0] = "ESI Non-Fatal Error", | ||
195 | }; | ||
196 | |||
197 | #define NERR_GLOBAL 0x44 | ||
198 | static const char *nerr_global_name[] = { | ||
199 | [31] = "Internal MCH Fatal Error", | ||
200 | [30] = "Intel QuickData Technology Device Fatal Error", | ||
201 | [29] = "FSB1 Fatal Error", | ||
202 | [28] = "FSB0 Fatal Error", | ||
203 | [27] = "FSB2 Fatal Error", | ||
204 | [26] = "FSB3 Fatal Error", | ||
205 | [25] = "Reserved", | ||
206 | [24] = "FBD Channel 0,1,2 or 3 Fatal Error", | ||
207 | [23] = "PCI Express Device 7 Fatal Error", | ||
208 | [22] = "PCI Express Device 6 Fatal Error", | ||
209 | [21] = "PCI Express Device 5 Fatal Error", | ||
210 | [20] = "PCI Express Device 4 Fatal Error", | ||
211 | [19] = "PCI Express Device 3 Fatal Error", | ||
212 | [18] = "PCI Express Device 2 Fatal Error", | ||
213 | [17] = "PCI Express Device 1 Fatal Error", | ||
214 | [16] = "ESI Fatal Error", | ||
215 | [15] = "Internal MCH Non-Fatal Error", | ||
216 | [14] = "Intel QuickData Technology Device Non Fatal Error", | ||
217 | [13] = "FSB1 Non-Fatal Error", | ||
218 | [12] = "FSB0 Non-Fatal Error", | ||
219 | [11] = "FSB2 Non-Fatal Error", | ||
220 | [10] = "FSB3 Non-Fatal Error", | ||
221 | [9] = "Reserved", | ||
222 | [8] = "FBD Channel 0,1, 2 or 3 Non-Fatal Error", | ||
223 | [7] = "PCI Express Device 7 Non-Fatal Error", | ||
224 | [6] = "PCI Express Device 6 Non-Fatal Error", | ||
225 | [5] = "PCI Express Device 5 Non-Fatal Error", | ||
226 | [4] = "PCI Express Device 4 Non-Fatal Error", | ||
227 | [3] = "PCI Express Device 3 Non-Fatal Error", | ||
228 | [2] = "PCI Express Device 2 Non-Fatal Error", | ||
229 | [1] = "PCI Express Device 1 Non-Fatal Error", | ||
230 | [0] = "ESI Non-Fatal Error", | ||
231 | }; | ||
232 | |||
223 | #if 0 | 233 | #if 0 |
224 | 234 | ||
225 | /* | 235 | /* |