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authorMauro Carvalho Chehab <mchehab@redhat.com>2009-07-10 17:39:53 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2010-05-10 10:44:51 -0400
commitd1fd4fb69eeeb7db0693df58b9116db498d5bfe1 (patch)
treee3870ec2d0c20804c2865a67c606acf8a736c01c /drivers/edac
parent5707b24a50b40582226618c56692af932db9fe02 (diff)
i7core_edac: Add a code to probe Xeon 55xx bus
This code changes the detection procedure of i7core_edac. Instead of directly probing for MC registers, it probes for another register found on Nehalem. If found, it tries to pick the first MC PCI BUS. This should work fine with Xeon 35xx, but, on Xeon 55xx, this is at bus 254 and 255 that are not properly detected by the non-legacy PCI methods. The new detection code scans specifically at buses 254 and 255 for the Xeon 55xx devices. This code has not tested yet. After working, a change at the code will be needed, since the i7core is not yet ready for working with 2 sets of MC. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/i7core_edac.c17
1 files changed, 13 insertions, 4 deletions
diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c
index 26cd5c924d56..eec0c13c0205 100644
--- a/drivers/edac/i7core_edac.c
+++ b/drivers/edac/i7core_edac.c
@@ -221,15 +221,15 @@ struct i7core_dev_info {
221 .dev_id = (device_id) 221 .dev_id = (device_id)
222 222
223struct pci_id_descr pci_devs[] = { 223struct pci_id_descr pci_devs[] = {
224 /* Generic Non-core registers */
225 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NOCORE) },
226
224 /* Memory controller */ 227 /* Memory controller */
225 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) }, 228 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
226 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) }, 229 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
227 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS) }, /* if RDIMM is supported */ 230 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS) }, /* if RDIMM is supported */
228 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) }, 231 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
229 232
230 /* Generic Non-core registers */
231 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NOCORE) },
232
233 /* Channel 0 */ 233 /* Channel 0 */
234 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) }, 234 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
235 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) }, 235 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
@@ -255,7 +255,7 @@ struct pci_id_descr pci_devs[] = {
255 * This should match the first device at pci_devs table 255 * This should match the first device at pci_devs table
256 */ 256 */
257static const struct pci_device_id i7core_pci_tbl[] __devinitdata = { 257static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
258 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7_MCR)}, 258 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
259 {0,} /* 0 terminated list. */ 259 {0,} /* 0 terminated list. */
260}; 260};
261 261
@@ -1069,6 +1069,15 @@ static int i7core_get_devices(void)
1069 for (i = 0; i < N_DEVS; i++) { 1069 for (i = 0; i < N_DEVS; i++) {
1070 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 1070 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1071 pci_devs[i].dev_id, NULL); 1071 pci_devs[i].dev_id, NULL);
1072
1073 if (!pdev && !i) {
1074 pcibios_scan_specific_bus(254);
1075 pcibios_scan_specific_bus(255);
1076
1077 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1078 pci_devs[i].dev_id, NULL);
1079 }
1080
1072 if (likely(pdev)) 1081 if (likely(pdev))
1073 pci_devs[i].pdev = pdev; 1082 pci_devs[i].pdev = pdev;
1074 else { 1083 else {