diff options
author | Borislav Petkov <borislav.petkov@amd.com> | 2009-09-24 05:05:30 -0400 |
---|---|---|
committer | Borislav Petkov <borislav.petkov@amd.com> | 2009-10-07 10:51:28 -0400 |
commit | 94baaee4947d84809b289d5ca03677525ffc6da9 (patch) | |
tree | 61134e2d9fc2e639d4dfc4ec50f90730d2f21f75 /drivers/edac | |
parent | 66216a7a15e75d517dddd0ac6514924b15071e4c (diff) |
amd64_edac: beef up DRAM error injection
When injecting DRAM ECC errors (F3xBC_x8), EccVector[15:0] is a bitmask
of which bits should be error injected when written to and holds the
payload of 16-bit DRAM word when read, respectively.
Add /sysfs members to show the DRAM ECC section/word/vector.
Fail wrong injection values entered over /sysfs instead of truncating
them.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r-- | drivers/edac/amd64_edac.h | 6 | ||||
-rw-r--r-- | drivers/edac/amd64_edac_inj.c | 49 |
2 files changed, 45 insertions, 10 deletions
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 64193927a05a..c6f359a85207 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h | |||
@@ -372,13 +372,11 @@ enum { | |||
372 | 372 | ||
373 | #define SET_NB_DRAM_INJECTION_WRITE(word, bits) \ | 373 | #define SET_NB_DRAM_INJECTION_WRITE(word, bits) \ |
374 | (BIT(((word) & 0xF) + 20) | \ | 374 | (BIT(((word) & 0xF) + 20) | \ |
375 | BIT(17) | \ | 375 | BIT(17) | bits) |
376 | ((bits) & 0xF)) | ||
377 | 376 | ||
378 | #define SET_NB_DRAM_INJECTION_READ(word, bits) \ | 377 | #define SET_NB_DRAM_INJECTION_READ(word, bits) \ |
379 | (BIT(((word) & 0xF) + 20) | \ | 378 | (BIT(((word) & 0xF) + 20) | \ |
380 | BIT(16) | \ | 379 | BIT(16) | bits) |
381 | ((bits) & 0xF)) | ||
382 | 380 | ||
383 | #define K8_NBCAP 0xE8 | 381 | #define K8_NBCAP 0xE8 |
384 | #define K8_NBCAP_CORES (BIT(12)|BIT(13)) | 382 | #define K8_NBCAP_CORES (BIT(12)|BIT(13)) |
diff --git a/drivers/edac/amd64_edac_inj.c b/drivers/edac/amd64_edac_inj.c index d3675b76b3a7..29f1f7a612d9 100644 --- a/drivers/edac/amd64_edac_inj.c +++ b/drivers/edac/amd64_edac_inj.c | |||
@@ -1,5 +1,11 @@ | |||
1 | #include "amd64_edac.h" | 1 | #include "amd64_edac.h" |
2 | 2 | ||
3 | static ssize_t amd64_inject_section_show(struct mem_ctl_info *mci, char *buf) | ||
4 | { | ||
5 | struct amd64_pvt *pvt = mci->pvt_info; | ||
6 | return sprintf(buf, "0x%x\n", pvt->injection.section); | ||
7 | } | ||
8 | |||
3 | /* | 9 | /* |
4 | * store error injection section value which refers to one of 4 16-byte sections | 10 | * store error injection section value which refers to one of 4 16-byte sections |
5 | * within a 64-byte cacheline | 11 | * within a 64-byte cacheline |
@@ -15,12 +21,26 @@ static ssize_t amd64_inject_section_store(struct mem_ctl_info *mci, | |||
15 | 21 | ||
16 | ret = strict_strtoul(data, 10, &value); | 22 | ret = strict_strtoul(data, 10, &value); |
17 | if (ret != -EINVAL) { | 23 | if (ret != -EINVAL) { |
24 | |||
25 | if (value > 3) { | ||
26 | amd64_printk(KERN_WARNING, | ||
27 | "%s: invalid section 0x%lx\n", | ||
28 | __func__, value); | ||
29 | return -EINVAL; | ||
30 | } | ||
31 | |||
18 | pvt->injection.section = (u32) value; | 32 | pvt->injection.section = (u32) value; |
19 | return count; | 33 | return count; |
20 | } | 34 | } |
21 | return ret; | 35 | return ret; |
22 | } | 36 | } |
23 | 37 | ||
38 | static ssize_t amd64_inject_word_show(struct mem_ctl_info *mci, char *buf) | ||
39 | { | ||
40 | struct amd64_pvt *pvt = mci->pvt_info; | ||
41 | return sprintf(buf, "0x%x\n", pvt->injection.word); | ||
42 | } | ||
43 | |||
24 | /* | 44 | /* |
25 | * store error injection word value which refers to one of 9 16-bit word of the | 45 | * store error injection word value which refers to one of 9 16-bit word of the |
26 | * 16-byte (128-bit + ECC bits) section | 46 | * 16-byte (128-bit + ECC bits) section |
@@ -37,14 +57,25 @@ static ssize_t amd64_inject_word_store(struct mem_ctl_info *mci, | |||
37 | ret = strict_strtoul(data, 10, &value); | 57 | ret = strict_strtoul(data, 10, &value); |
38 | if (ret != -EINVAL) { | 58 | if (ret != -EINVAL) { |
39 | 59 | ||
40 | value = (value <= 8) ? value : 0; | 60 | if (value > 8) { |
41 | pvt->injection.word = (u32) value; | 61 | amd64_printk(KERN_WARNING, |
62 | "%s: invalid word 0x%lx\n", | ||
63 | __func__, value); | ||
64 | return -EINVAL; | ||
65 | } | ||
42 | 66 | ||
67 | pvt->injection.word = (u32) value; | ||
43 | return count; | 68 | return count; |
44 | } | 69 | } |
45 | return ret; | 70 | return ret; |
46 | } | 71 | } |
47 | 72 | ||
73 | static ssize_t amd64_inject_ecc_vector_show(struct mem_ctl_info *mci, char *buf) | ||
74 | { | ||
75 | struct amd64_pvt *pvt = mci->pvt_info; | ||
76 | return sprintf(buf, "0x%x\n", pvt->injection.bit_map); | ||
77 | } | ||
78 | |||
48 | /* | 79 | /* |
49 | * store 16 bit error injection vector which enables injecting errors to the | 80 | * store 16 bit error injection vector which enables injecting errors to the |
50 | * corresponding bit within the error injection word above. When used during a | 81 | * corresponding bit within the error injection word above. When used during a |
@@ -60,8 +91,14 @@ static ssize_t amd64_inject_ecc_vector_store(struct mem_ctl_info *mci, | |||
60 | ret = strict_strtoul(data, 16, &value); | 91 | ret = strict_strtoul(data, 16, &value); |
61 | if (ret != -EINVAL) { | 92 | if (ret != -EINVAL) { |
62 | 93 | ||
63 | pvt->injection.bit_map = (u32) value & 0xFFFF; | 94 | if (value & 0xFFFF0000) { |
95 | amd64_printk(KERN_WARNING, | ||
96 | "%s: invalid EccVector: 0x%lx\n", | ||
97 | __func__, value); | ||
98 | return -EINVAL; | ||
99 | } | ||
64 | 100 | ||
101 | pvt->injection.bit_map = (u32) value; | ||
65 | return count; | 102 | return count; |
66 | } | 103 | } |
67 | return ret; | 104 | return ret; |
@@ -147,7 +184,7 @@ struct mcidev_sysfs_attribute amd64_inj_attrs[] = { | |||
147 | .name = "inject_section", | 184 | .name = "inject_section", |
148 | .mode = (S_IRUGO | S_IWUSR) | 185 | .mode = (S_IRUGO | S_IWUSR) |
149 | }, | 186 | }, |
150 | .show = NULL, | 187 | .show = amd64_inject_section_show, |
151 | .store = amd64_inject_section_store, | 188 | .store = amd64_inject_section_store, |
152 | }, | 189 | }, |
153 | { | 190 | { |
@@ -155,7 +192,7 @@ struct mcidev_sysfs_attribute amd64_inj_attrs[] = { | |||
155 | .name = "inject_word", | 192 | .name = "inject_word", |
156 | .mode = (S_IRUGO | S_IWUSR) | 193 | .mode = (S_IRUGO | S_IWUSR) |
157 | }, | 194 | }, |
158 | .show = NULL, | 195 | .show = amd64_inject_word_show, |
159 | .store = amd64_inject_word_store, | 196 | .store = amd64_inject_word_store, |
160 | }, | 197 | }, |
161 | { | 198 | { |
@@ -163,7 +200,7 @@ struct mcidev_sysfs_attribute amd64_inj_attrs[] = { | |||
163 | .name = "inject_ecc_vector", | 200 | .name = "inject_ecc_vector", |
164 | .mode = (S_IRUGO | S_IWUSR) | 201 | .mode = (S_IRUGO | S_IWUSR) |
165 | }, | 202 | }, |
166 | .show = NULL, | 203 | .show = amd64_inject_ecc_vector_show, |
167 | .store = amd64_inject_ecc_vector_store, | 204 | .store = amd64_inject_ecc_vector_store, |
168 | }, | 205 | }, |
169 | { | 206 | { |