aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/edac
diff options
context:
space:
mode:
authorBorislav Petkov <borislav.petkov@amd.com>2009-10-16 13:55:49 -0400
committerBorislav Petkov <borislav.petkov@amd.com>2009-12-07 13:14:29 -0500
commitd16149e8c378ab7011e600980af51d2477aa5307 (patch)
treee2b28d69271d0c5afc11398ec5e97787b98ecc70 /drivers/edac
parent8566c4df1690f3862ae338a4c533f4bb5a863f9a (diff)
amd64_edac: cleanup f10_early_channel_count
Do not read DCLR[01] again since this is done in amd64_read_mc_registers() earlier. There can be more than two physical DIMMs present so clamp the channels value to max 2. Also, do not report DCT data width - it is also done earlier. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/amd64_edac.c18
1 files changed, 7 insertions, 11 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index c6d1aed2943f..ed9b07a4cf8f 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1204,28 +1204,21 @@ static int f10_early_channel_count(struct amd64_pvt *pvt)
1204 int i, j, channels = 0; 1204 int i, j, channels = 0;
1205 u32 dbam; 1205 u32 dbam;
1206 1206
1207 if (amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0))
1208 goto err_reg;
1209
1210 if (amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_1, &pvt->dclr1))
1211 goto err_reg;
1212
1213 /* If we are in 128 bit mode, then we are using 2 channels */ 1207 /* If we are in 128 bit mode, then we are using 2 channels */
1214 if (pvt->dclr0 & F10_WIDTH_128) { 1208 if (pvt->dclr0 & F10_WIDTH_128) {
1215 debugf0("Data WIDTH is 128 bits - 2 channels\n");
1216 channels = 2; 1209 channels = 2;
1217 return channels; 1210 return channels;
1218 } 1211 }
1219 1212
1220 /* 1213 /*
1221 * Need to check if in UN-ganged mode: In such, there are 2 channels, 1214 * Need to check if in unganged mode: In such, there are 2 channels,
1222 * but they are NOT in 128 bit mode and thus the above 'dcl0' status bit 1215 * but they are not in 128 bit mode and thus the above 'dclr0' status
1223 * will be OFF. 1216 * bit will be OFF.
1224 * 1217 *
1225 * Need to check DCT0[0] and DCT1[0] to see if only one of them has 1218 * Need to check DCT0[0] and DCT1[0] to see if only one of them has
1226 * their CSEnable bit on. If so, then SINGLE DIMM case. 1219 * their CSEnable bit on. If so, then SINGLE DIMM case.
1227 */ 1220 */
1228 debugf0("Data WIDTH is NOT 128 bits - need more decoding\n"); 1221 debugf0("Data width is not 128 bits - need more decoding\n");
1229 1222
1230 /* 1223 /*
1231 * Check DRAM Bank Address Mapping values for each DIMM to see if there 1224 * Check DRAM Bank Address Mapping values for each DIMM to see if there
@@ -1244,6 +1237,9 @@ static int f10_early_channel_count(struct amd64_pvt *pvt)
1244 } 1237 }
1245 } 1238 }
1246 1239
1240 if (channels > 2)
1241 channels = 2;
1242
1247 debugf0("MCT channel count: %d\n", channels); 1243 debugf0("MCT channel count: %d\n", channels);
1248 1244
1249 return channels; 1245 return channels;