diff options
author | Borislav Petkov <borislav.petkov@amd.com> | 2010-09-17 13:11:47 -0400 |
---|---|---|
committer | Borislav Petkov <borislav.petkov@amd.com> | 2011-01-07 05:54:12 -0500 |
commit | 2be64bfac71378e1aa8c20031a499bd55e391244 (patch) | |
tree | e9eb0cb97d4262e2674e34865a4ee01504199086 /drivers/edac | |
parent | 3c0eee3fe6a3a1c745379547c7e7c904aa64f6d5 (diff) |
EDAC, MCE: Select extended error code mask
F15h enlarges the extended error code of an MCE to a 5-bit field
(MCi_STATUS[20:16]). Add a mask variable which default 0xf is overridden
on F15h.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r-- | drivers/edac/mce_amd.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index c0181093b490..01853eed2019 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c | |||
@@ -5,6 +5,7 @@ | |||
5 | 5 | ||
6 | static struct amd_decoder_ops *fam_ops; | 6 | static struct amd_decoder_ops *fam_ops; |
7 | 7 | ||
8 | static u8 xec_mask = 0xf; | ||
8 | static u8 nb_err_cpumask = 0xf; | 9 | static u8 nb_err_cpumask = 0xf; |
9 | 10 | ||
10 | static bool report_gart_errors; | 11 | static bool report_gart_errors; |
@@ -172,7 +173,7 @@ static bool f14h_dc_mce(u16 ec) | |||
172 | static void amd_decode_dc_mce(struct mce *m) | 173 | static void amd_decode_dc_mce(struct mce *m) |
173 | { | 174 | { |
174 | u16 ec = m->status & 0xffff; | 175 | u16 ec = m->status & 0xffff; |
175 | u8 xec = (m->status >> 16) & 0xf; | 176 | u8 xec = (m->status >> 16) & xec_mask; |
176 | 177 | ||
177 | pr_emerg(HW_ERR "Data Cache Error: "); | 178 | pr_emerg(HW_ERR "Data Cache Error: "); |
178 | 179 | ||
@@ -257,7 +258,7 @@ static bool f14h_ic_mce(u16 ec) | |||
257 | static void amd_decode_ic_mce(struct mce *m) | 258 | static void amd_decode_ic_mce(struct mce *m) |
258 | { | 259 | { |
259 | u16 ec = m->status & 0xffff; | 260 | u16 ec = m->status & 0xffff; |
260 | u8 xec = (m->status >> 16) & 0xf; | 261 | u8 xec = (m->status >> 16) & xec_mask; |
261 | 262 | ||
262 | pr_emerg(HW_ERR "Instruction Cache Error: "); | 263 | pr_emerg(HW_ERR "Instruction Cache Error: "); |
263 | 264 | ||
@@ -277,7 +278,7 @@ static void amd_decode_ic_mce(struct mce *m) | |||
277 | static void amd_decode_bu_mce(struct mce *m) | 278 | static void amd_decode_bu_mce(struct mce *m) |
278 | { | 279 | { |
279 | u32 ec = m->status & 0xffff; | 280 | u32 ec = m->status & 0xffff; |
280 | u32 xec = (m->status >> 16) & 0xf; | 281 | u32 xec = (m->status >> 16) & xec_mask; |
281 | 282 | ||
282 | pr_emerg(HW_ERR "Bus Unit Error"); | 283 | pr_emerg(HW_ERR "Bus Unit Error"); |
283 | 284 | ||
@@ -319,7 +320,7 @@ wrong_bu_mce: | |||
319 | static void amd_decode_ls_mce(struct mce *m) | 320 | static void amd_decode_ls_mce(struct mce *m) |
320 | { | 321 | { |
321 | u16 ec = m->status & 0xffff; | 322 | u16 ec = m->status & 0xffff; |
322 | u8 xec = (m->status >> 16) & 0xf; | 323 | u8 xec = (m->status >> 16) & xec_mask; |
323 | 324 | ||
324 | if (boot_cpu_data.x86 == 0x14) { | 325 | if (boot_cpu_data.x86 == 0x14) { |
325 | pr_emerg("You shouldn't be seeing an LS MCE on this cpu family," | 326 | pr_emerg("You shouldn't be seeing an LS MCE on this cpu family," |
@@ -651,6 +652,10 @@ static int __init mce_amd_init(void) | |||
651 | fam_ops->nb_mce = nb_noop_mce; | 652 | fam_ops->nb_mce = nb_noop_mce; |
652 | break; | 653 | break; |
653 | 654 | ||
655 | case 0x15: | ||
656 | xec_mask = 0x1f; | ||
657 | break; | ||
658 | |||
654 | default: | 659 | default: |
655 | printk(KERN_WARNING "Huh? What family is that: %d?!\n", | 660 | printk(KERN_WARNING "Huh? What family is that: %d?!\n", |
656 | boot_cpu_data.x86); | 661 | boot_cpu_data.x86); |