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authorBorislav Petkov <borislav.petkov@amd.com>2011-08-10 08:43:30 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-08-10 13:57:42 -0400
commitaf9d220bac41dc3201893e1601cc7c44f7da4498 (patch)
tree14ad1f95320271a63057a6bc2bf219cc0ea926e5 /drivers/edac
parentf2c0d0266cc5eb36a4aa44944b4096ec121490aa (diff)
EDAC: Correct Kconfig dependencies
Both AMD and Intel i7 EDAC drivers use MCE features and are thus dependent of this functionality present in the kernel. Express this in Kconfig so that randconfig builds don't break. Reported-by: Randy Dunlap <rdunlap@xenotime.net> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Acked-by: Randy Dunlap <rdunlap@xenotime.net> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/Kconfig5
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index af1a17d42bd7..c422fead0855 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -41,7 +41,7 @@ config EDAC_DEBUG
41 41
42config EDAC_DECODE_MCE 42config EDAC_DECODE_MCE
43 tristate "Decode MCEs in human-readable form (only on AMD for now)" 43 tristate "Decode MCEs in human-readable form (only on AMD for now)"
44 depends on CPU_SUP_AMD && X86_MCE 44 depends on CPU_SUP_AMD && X86_MCE_AMD
45 default y 45 default y
46 ---help--- 46 ---help---
47 Enable this option if you want to decode Machine Check Exceptions 47 Enable this option if you want to decode Machine Check Exceptions
@@ -173,8 +173,7 @@ config EDAC_I5400
173 173
174config EDAC_I7CORE 174config EDAC_I7CORE
175 tristate "Intel i7 Core (Nehalem) processors" 175 tristate "Intel i7 Core (Nehalem) processors"
176 depends on EDAC_MM_EDAC && PCI && X86 176 depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
177 select EDAC_MCE
178 help 177 help
179 Support for error detection and correction the Intel 178 Support for error detection and correction the Intel
180 i7 Core (Nehalem) Integrated Memory Controller that exists on 179 i7 Core (Nehalem) Integrated Memory Controller that exists on