diff options
author | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-07-29 20:11:05 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-07-29 20:11:05 -0400 |
commit | c2078e4c9120e7b38b1a02cd9fc6dd4f792110bf (patch) | |
tree | a30b29c0bf8cf2288a32ceaeb75013cb0b5d5865 /drivers/edac/sb_edac.c | |
parent | 73bcc49959e4e40911dd0dd634bf1b353827df66 (diff) | |
parent | f58d0dee07fe6328f775669eb6aa3a123efad6c2 (diff) |
Merge branch 'devel'
* devel: (33 commits)
edac i5000, i5400: fix pointer math in i5000_get_mc_regs()
edac: allow specifying the error count with fake_inject
edac: add support for Calxeda highbank L2 cache ecc
edac: add support for Calxeda highbank memory controller
edac: create top-level debugfs directory
sb_edac: properly handle error count
i7core_edac: properly handle error count
edac: edac_mc_handle_error(): add an error_count parameter
edac: remove arch-specific parameter for the error handler
amd64_edac: Don't pass driver name as an error parameter
edac_mc: check for allocation failure in edac_mc_alloc()
edac: Increase version to 3.0.0
edac_mc: Cleanup per-dimm_info debug messages
edac: Convert debugfX to edac_dbg(X,
edac: Use more normal debugging macro style
edac: Don't add __func__ or __FILE__ for debugf[0-9] msgs
Edac: Add ABI Documentation for the new device nodes
edac: move documentation ABI to ABI/testing/sysfs-devices-edac
i7core_edac: change the mem allocation scheme to make Documentation/kobject.txt happy
edac: change the mem allocation scheme to make Documentation/kobject.txt happy
...
Diffstat (limited to 'drivers/edac/sb_edac.c')
-rw-r--r-- | drivers/edac/sb_edac.c | 257 |
1 files changed, 126 insertions, 131 deletions
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c index 36ad17e79d61..f3b1f9fafa4b 100644 --- a/drivers/edac/sb_edac.c +++ b/drivers/edac/sb_edac.c | |||
@@ -381,8 +381,8 @@ static inline int numrank(u32 mtr) | |||
381 | int ranks = (1 << RANK_CNT_BITS(mtr)); | 381 | int ranks = (1 << RANK_CNT_BITS(mtr)); |
382 | 382 | ||
383 | if (ranks > 4) { | 383 | if (ranks > 4) { |
384 | debugf0("Invalid number of ranks: %d (max = 4) raw value = %x (%04x)", | 384 | edac_dbg(0, "Invalid number of ranks: %d (max = 4) raw value = %x (%04x)\n", |
385 | ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr); | 385 | ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr); |
386 | return -EINVAL; | 386 | return -EINVAL; |
387 | } | 387 | } |
388 | 388 | ||
@@ -394,8 +394,8 @@ static inline int numrow(u32 mtr) | |||
394 | int rows = (RANK_WIDTH_BITS(mtr) + 12); | 394 | int rows = (RANK_WIDTH_BITS(mtr) + 12); |
395 | 395 | ||
396 | if (rows < 13 || rows > 18) { | 396 | if (rows < 13 || rows > 18) { |
397 | debugf0("Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)", | 397 | edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n", |
398 | rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); | 398 | rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); |
399 | return -EINVAL; | 399 | return -EINVAL; |
400 | } | 400 | } |
401 | 401 | ||
@@ -407,8 +407,8 @@ static inline int numcol(u32 mtr) | |||
407 | int cols = (COL_WIDTH_BITS(mtr) + 10); | 407 | int cols = (COL_WIDTH_BITS(mtr) + 10); |
408 | 408 | ||
409 | if (cols > 12) { | 409 | if (cols > 12) { |
410 | debugf0("Invalid number of cols: %d (max = 4) raw value = %x (%04x)", | 410 | edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n", |
411 | cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); | 411 | cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); |
412 | return -EINVAL; | 412 | return -EINVAL; |
413 | } | 413 | } |
414 | 414 | ||
@@ -475,8 +475,8 @@ static struct pci_dev *get_pdev_slot_func(u8 bus, unsigned slot, | |||
475 | 475 | ||
476 | if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot && | 476 | if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot && |
477 | PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) { | 477 | PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) { |
478 | debugf1("Associated %02x.%02x.%d with %p\n", | 478 | edac_dbg(1, "Associated %02x.%02x.%d with %p\n", |
479 | bus, slot, func, sbridge_dev->pdev[i]); | 479 | bus, slot, func, sbridge_dev->pdev[i]); |
480 | return sbridge_dev->pdev[i]; | 480 | return sbridge_dev->pdev[i]; |
481 | } | 481 | } |
482 | } | 482 | } |
@@ -523,45 +523,45 @@ static int get_dimm_config(struct mem_ctl_info *mci) | |||
523 | 523 | ||
524 | pci_read_config_dword(pvt->pci_br, SAD_CONTROL, ®); | 524 | pci_read_config_dword(pvt->pci_br, SAD_CONTROL, ®); |
525 | pvt->sbridge_dev->node_id = NODE_ID(reg); | 525 | pvt->sbridge_dev->node_id = NODE_ID(reg); |
526 | debugf0("mc#%d: Node ID: %d, source ID: %d\n", | 526 | edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n", |
527 | pvt->sbridge_dev->mc, | 527 | pvt->sbridge_dev->mc, |
528 | pvt->sbridge_dev->node_id, | 528 | pvt->sbridge_dev->node_id, |
529 | pvt->sbridge_dev->source_id); | 529 | pvt->sbridge_dev->source_id); |
530 | 530 | ||
531 | pci_read_config_dword(pvt->pci_ras, RASENABLES, ®); | 531 | pci_read_config_dword(pvt->pci_ras, RASENABLES, ®); |
532 | if (IS_MIRROR_ENABLED(reg)) { | 532 | if (IS_MIRROR_ENABLED(reg)) { |
533 | debugf0("Memory mirror is enabled\n"); | 533 | edac_dbg(0, "Memory mirror is enabled\n"); |
534 | pvt->is_mirrored = true; | 534 | pvt->is_mirrored = true; |
535 | } else { | 535 | } else { |
536 | debugf0("Memory mirror is disabled\n"); | 536 | edac_dbg(0, "Memory mirror is disabled\n"); |
537 | pvt->is_mirrored = false; | 537 | pvt->is_mirrored = false; |
538 | } | 538 | } |
539 | 539 | ||
540 | pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr); | 540 | pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr); |
541 | if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { | 541 | if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { |
542 | debugf0("Lockstep is enabled\n"); | 542 | edac_dbg(0, "Lockstep is enabled\n"); |
543 | mode = EDAC_S8ECD8ED; | 543 | mode = EDAC_S8ECD8ED; |
544 | pvt->is_lockstep = true; | 544 | pvt->is_lockstep = true; |
545 | } else { | 545 | } else { |
546 | debugf0("Lockstep is disabled\n"); | 546 | edac_dbg(0, "Lockstep is disabled\n"); |
547 | mode = EDAC_S4ECD4ED; | 547 | mode = EDAC_S4ECD4ED; |
548 | pvt->is_lockstep = false; | 548 | pvt->is_lockstep = false; |
549 | } | 549 | } |
550 | if (IS_CLOSE_PG(pvt->info.mcmtr)) { | 550 | if (IS_CLOSE_PG(pvt->info.mcmtr)) { |
551 | debugf0("address map is on closed page mode\n"); | 551 | edac_dbg(0, "address map is on closed page mode\n"); |
552 | pvt->is_close_pg = true; | 552 | pvt->is_close_pg = true; |
553 | } else { | 553 | } else { |
554 | debugf0("address map is on open page mode\n"); | 554 | edac_dbg(0, "address map is on open page mode\n"); |
555 | pvt->is_close_pg = false; | 555 | pvt->is_close_pg = false; |
556 | } | 556 | } |
557 | 557 | ||
558 | pci_read_config_dword(pvt->pci_ddrio, RANK_CFG_A, ®); | 558 | pci_read_config_dword(pvt->pci_ddrio, RANK_CFG_A, ®); |
559 | if (IS_RDIMM_ENABLED(reg)) { | 559 | if (IS_RDIMM_ENABLED(reg)) { |
560 | /* FIXME: Can also be LRDIMM */ | 560 | /* FIXME: Can also be LRDIMM */ |
561 | debugf0("Memory is registered\n"); | 561 | edac_dbg(0, "Memory is registered\n"); |
562 | mtype = MEM_RDDR3; | 562 | mtype = MEM_RDDR3; |
563 | } else { | 563 | } else { |
564 | debugf0("Memory is unregistered\n"); | 564 | edac_dbg(0, "Memory is unregistered\n"); |
565 | mtype = MEM_DDR3; | 565 | mtype = MEM_DDR3; |
566 | } | 566 | } |
567 | 567 | ||
@@ -576,7 +576,7 @@ static int get_dimm_config(struct mem_ctl_info *mci) | |||
576 | i, j, 0); | 576 | i, j, 0); |
577 | pci_read_config_dword(pvt->pci_tad[i], | 577 | pci_read_config_dword(pvt->pci_tad[i], |
578 | mtr_regs[j], &mtr); | 578 | mtr_regs[j], &mtr); |
579 | debugf4("Channel #%d MTR%d = %x\n", i, j, mtr); | 579 | edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr); |
580 | if (IS_DIMM_PRESENT(mtr)) { | 580 | if (IS_DIMM_PRESENT(mtr)) { |
581 | pvt->channel[i].dimms++; | 581 | pvt->channel[i].dimms++; |
582 | 582 | ||
@@ -588,10 +588,10 @@ static int get_dimm_config(struct mem_ctl_info *mci) | |||
588 | size = (rows * cols * banks * ranks) >> (20 - 3); | 588 | size = (rows * cols * banks * ranks) >> (20 - 3); |
589 | npages = MiB_TO_PAGES(size); | 589 | npages = MiB_TO_PAGES(size); |
590 | 590 | ||
591 | debugf0("mc#%d: channel %d, dimm %d, %d Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", | 591 | edac_dbg(0, "mc#%d: channel %d, dimm %d, %d Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", |
592 | pvt->sbridge_dev->mc, i, j, | 592 | pvt->sbridge_dev->mc, i, j, |
593 | size, npages, | 593 | size, npages, |
594 | banks, ranks, rows, cols); | 594 | banks, ranks, rows, cols); |
595 | 595 | ||
596 | dimm->nr_pages = npages; | 596 | dimm->nr_pages = npages; |
597 | dimm->grain = 32; | 597 | dimm->grain = 32; |
@@ -629,8 +629,7 @@ static void get_memory_layout(const struct mem_ctl_info *mci) | |||
629 | tmp_mb = (1 + pvt->tolm) >> 20; | 629 | tmp_mb = (1 + pvt->tolm) >> 20; |
630 | 630 | ||
631 | mb = div_u64_rem(tmp_mb, 1000, &kb); | 631 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
632 | debugf0("TOLM: %u.%03u GB (0x%016Lx)\n", | 632 | edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tolm); |
633 | mb, kb, (u64)pvt->tolm); | ||
634 | 633 | ||
635 | /* Address range is already 45:25 */ | 634 | /* Address range is already 45:25 */ |
636 | pci_read_config_dword(pvt->pci_sad1, TOHM, | 635 | pci_read_config_dword(pvt->pci_sad1, TOHM, |
@@ -639,8 +638,7 @@ static void get_memory_layout(const struct mem_ctl_info *mci) | |||
639 | tmp_mb = (1 + pvt->tohm) >> 20; | 638 | tmp_mb = (1 + pvt->tohm) >> 20; |
640 | 639 | ||
641 | mb = div_u64_rem(tmp_mb, 1000, &kb); | 640 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
642 | debugf0("TOHM: %u.%03u GB (0x%016Lx)", | 641 | edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)", mb, kb, (u64)pvt->tohm); |
643 | mb, kb, (u64)pvt->tohm); | ||
644 | 642 | ||
645 | /* | 643 | /* |
646 | * Step 2) Get SAD range and SAD Interleave list | 644 | * Step 2) Get SAD range and SAD Interleave list |
@@ -663,13 +661,13 @@ static void get_memory_layout(const struct mem_ctl_info *mci) | |||
663 | 661 | ||
664 | tmp_mb = (limit + 1) >> 20; | 662 | tmp_mb = (limit + 1) >> 20; |
665 | mb = div_u64_rem(tmp_mb, 1000, &kb); | 663 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
666 | debugf0("SAD#%d %s up to %u.%03u GB (0x%016Lx) %s reg=0x%08x\n", | 664 | edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n", |
667 | n_sads, | 665 | n_sads, |
668 | get_dram_attr(reg), | 666 | get_dram_attr(reg), |
669 | mb, kb, | 667 | mb, kb, |
670 | ((u64)tmp_mb) << 20L, | 668 | ((u64)tmp_mb) << 20L, |
671 | INTERLEAVE_MODE(reg) ? "Interleave: 8:6" : "Interleave: [8:6]XOR[18:16]", | 669 | INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]", |
672 | reg); | 670 | reg); |
673 | prv = limit; | 671 | prv = limit; |
674 | 672 | ||
675 | pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads], | 673 | pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads], |
@@ -679,8 +677,8 @@ static void get_memory_layout(const struct mem_ctl_info *mci) | |||
679 | if (j > 0 && sad_interl == sad_pkg(reg, j)) | 677 | if (j > 0 && sad_interl == sad_pkg(reg, j)) |
680 | break; | 678 | break; |
681 | 679 | ||
682 | debugf0("SAD#%d, interleave #%d: %d\n", | 680 | edac_dbg(0, "SAD#%d, interleave #%d: %d\n", |
683 | n_sads, j, sad_pkg(reg, j)); | 681 | n_sads, j, sad_pkg(reg, j)); |
684 | } | 682 | } |
685 | } | 683 | } |
686 | 684 | ||
@@ -697,16 +695,16 @@ static void get_memory_layout(const struct mem_ctl_info *mci) | |||
697 | tmp_mb = (limit + 1) >> 20; | 695 | tmp_mb = (limit + 1) >> 20; |
698 | 696 | ||
699 | mb = div_u64_rem(tmp_mb, 1000, &kb); | 697 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
700 | debugf0("TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", | 698 | edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", |
701 | n_tads, mb, kb, | 699 | n_tads, mb, kb, |
702 | ((u64)tmp_mb) << 20L, | 700 | ((u64)tmp_mb) << 20L, |
703 | (u32)TAD_SOCK(reg), | 701 | (u32)TAD_SOCK(reg), |
704 | (u32)TAD_CH(reg), | 702 | (u32)TAD_CH(reg), |
705 | (u32)TAD_TGT0(reg), | 703 | (u32)TAD_TGT0(reg), |
706 | (u32)TAD_TGT1(reg), | 704 | (u32)TAD_TGT1(reg), |
707 | (u32)TAD_TGT2(reg), | 705 | (u32)TAD_TGT2(reg), |
708 | (u32)TAD_TGT3(reg), | 706 | (u32)TAD_TGT3(reg), |
709 | reg); | 707 | reg); |
710 | prv = limit; | 708 | prv = limit; |
711 | } | 709 | } |
712 | 710 | ||
@@ -722,11 +720,11 @@ static void get_memory_layout(const struct mem_ctl_info *mci) | |||
722 | ®); | 720 | ®); |
723 | tmp_mb = TAD_OFFSET(reg) >> 20; | 721 | tmp_mb = TAD_OFFSET(reg) >> 20; |
724 | mb = div_u64_rem(tmp_mb, 1000, &kb); | 722 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
725 | debugf0("TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", | 723 | edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", |
726 | i, j, | 724 | i, j, |
727 | mb, kb, | 725 | mb, kb, |
728 | ((u64)tmp_mb) << 20L, | 726 | ((u64)tmp_mb) << 20L, |
729 | reg); | 727 | reg); |
730 | } | 728 | } |
731 | } | 729 | } |
732 | 730 | ||
@@ -747,12 +745,12 @@ static void get_memory_layout(const struct mem_ctl_info *mci) | |||
747 | tmp_mb = RIR_LIMIT(reg) >> 20; | 745 | tmp_mb = RIR_LIMIT(reg) >> 20; |
748 | rir_way = 1 << RIR_WAY(reg); | 746 | rir_way = 1 << RIR_WAY(reg); |
749 | mb = div_u64_rem(tmp_mb, 1000, &kb); | 747 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
750 | debugf0("CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", | 748 | edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", |
751 | i, j, | 749 | i, j, |
752 | mb, kb, | 750 | mb, kb, |
753 | ((u64)tmp_mb) << 20L, | 751 | ((u64)tmp_mb) << 20L, |
754 | rir_way, | 752 | rir_way, |
755 | reg); | 753 | reg); |
756 | 754 | ||
757 | for (k = 0; k < rir_way; k++) { | 755 | for (k = 0; k < rir_way; k++) { |
758 | pci_read_config_dword(pvt->pci_tad[i], | 756 | pci_read_config_dword(pvt->pci_tad[i], |
@@ -761,12 +759,12 @@ static void get_memory_layout(const struct mem_ctl_info *mci) | |||
761 | tmp_mb = RIR_OFFSET(reg) << 6; | 759 | tmp_mb = RIR_OFFSET(reg) << 6; |
762 | 760 | ||
763 | mb = div_u64_rem(tmp_mb, 1000, &kb); | 761 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
764 | debugf0("CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", | 762 | edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", |
765 | i, j, k, | 763 | i, j, k, |
766 | mb, kb, | 764 | mb, kb, |
767 | ((u64)tmp_mb) << 20L, | 765 | ((u64)tmp_mb) << 20L, |
768 | (u32)RIR_RNK_TGT(reg), | 766 | (u32)RIR_RNK_TGT(reg), |
769 | reg); | 767 | reg); |
770 | } | 768 | } |
771 | } | 769 | } |
772 | } | 770 | } |
@@ -853,16 +851,16 @@ static int get_memory_error_data(struct mem_ctl_info *mci, | |||
853 | if (sad_way > 0 && sad_interl == sad_pkg(reg, sad_way)) | 851 | if (sad_way > 0 && sad_interl == sad_pkg(reg, sad_way)) |
854 | break; | 852 | break; |
855 | sad_interleave[sad_way] = sad_pkg(reg, sad_way); | 853 | sad_interleave[sad_way] = sad_pkg(reg, sad_way); |
856 | debugf0("SAD interleave #%d: %d\n", | 854 | edac_dbg(0, "SAD interleave #%d: %d\n", |
857 | sad_way, sad_interleave[sad_way]); | 855 | sad_way, sad_interleave[sad_way]); |
858 | } | 856 | } |
859 | debugf0("mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", | 857 | edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", |
860 | pvt->sbridge_dev->mc, | 858 | pvt->sbridge_dev->mc, |
861 | n_sads, | 859 | n_sads, |
862 | addr, | 860 | addr, |
863 | limit, | 861 | limit, |
864 | sad_way + 7, | 862 | sad_way + 7, |
865 | interleave_mode ? "" : "XOR[18:16]"); | 863 | interleave_mode ? "" : "XOR[18:16]"); |
866 | if (interleave_mode) | 864 | if (interleave_mode) |
867 | idx = ((addr >> 6) ^ (addr >> 16)) & 7; | 865 | idx = ((addr >> 6) ^ (addr >> 16)) & 7; |
868 | else | 866 | else |
@@ -884,8 +882,8 @@ static int get_memory_error_data(struct mem_ctl_info *mci, | |||
884 | return -EINVAL; | 882 | return -EINVAL; |
885 | } | 883 | } |
886 | *socket = sad_interleave[idx]; | 884 | *socket = sad_interleave[idx]; |
887 | debugf0("SAD interleave index: %d (wayness %d) = CPU socket %d\n", | 885 | edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", |
888 | idx, sad_way, *socket); | 886 | idx, sad_way, *socket); |
889 | 887 | ||
890 | /* | 888 | /* |
891 | * Move to the proper node structure, in order to access the | 889 | * Move to the proper node structure, in order to access the |
@@ -972,16 +970,16 @@ static int get_memory_error_data(struct mem_ctl_info *mci, | |||
972 | 970 | ||
973 | offset = TAD_OFFSET(tad_offset); | 971 | offset = TAD_OFFSET(tad_offset); |
974 | 972 | ||
975 | debugf0("TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", | 973 | edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", |
976 | n_tads, | 974 | n_tads, |
977 | addr, | 975 | addr, |
978 | limit, | 976 | limit, |
979 | (u32)TAD_SOCK(reg), | 977 | (u32)TAD_SOCK(reg), |
980 | ch_way, | 978 | ch_way, |
981 | offset, | 979 | offset, |
982 | idx, | 980 | idx, |
983 | base_ch, | 981 | base_ch, |
984 | *channel_mask); | 982 | *channel_mask); |
985 | 983 | ||
986 | /* Calculate channel address */ | 984 | /* Calculate channel address */ |
987 | /* Remove the TAD offset */ | 985 | /* Remove the TAD offset */ |
@@ -1017,11 +1015,11 @@ static int get_memory_error_data(struct mem_ctl_info *mci, | |||
1017 | 1015 | ||
1018 | limit = RIR_LIMIT(reg); | 1016 | limit = RIR_LIMIT(reg); |
1019 | mb = div_u64_rem(limit >> 20, 1000, &kb); | 1017 | mb = div_u64_rem(limit >> 20, 1000, &kb); |
1020 | debugf0("RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", | 1018 | edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", |
1021 | n_rir, | 1019 | n_rir, |
1022 | mb, kb, | 1020 | mb, kb, |
1023 | limit, | 1021 | limit, |
1024 | 1 << RIR_WAY(reg)); | 1022 | 1 << RIR_WAY(reg)); |
1025 | if (ch_addr <= limit) | 1023 | if (ch_addr <= limit) |
1026 | break; | 1024 | break; |
1027 | } | 1025 | } |
@@ -1042,12 +1040,12 @@ static int get_memory_error_data(struct mem_ctl_info *mci, | |||
1042 | ®); | 1040 | ®); |
1043 | *rank = RIR_RNK_TGT(reg); | 1041 | *rank = RIR_RNK_TGT(reg); |
1044 | 1042 | ||
1045 | debugf0("RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", | 1043 | edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", |
1046 | n_rir, | 1044 | n_rir, |
1047 | ch_addr, | 1045 | ch_addr, |
1048 | limit, | 1046 | limit, |
1049 | rir_way, | 1047 | rir_way, |
1050 | idx); | 1048 | idx); |
1051 | 1049 | ||
1052 | return 0; | 1050 | return 0; |
1053 | } | 1051 | } |
@@ -1064,14 +1062,14 @@ static void sbridge_put_devices(struct sbridge_dev *sbridge_dev) | |||
1064 | { | 1062 | { |
1065 | int i; | 1063 | int i; |
1066 | 1064 | ||
1067 | debugf0(__FILE__ ": %s()\n", __func__); | 1065 | edac_dbg(0, "\n"); |
1068 | for (i = 0; i < sbridge_dev->n_devs; i++) { | 1066 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
1069 | struct pci_dev *pdev = sbridge_dev->pdev[i]; | 1067 | struct pci_dev *pdev = sbridge_dev->pdev[i]; |
1070 | if (!pdev) | 1068 | if (!pdev) |
1071 | continue; | 1069 | continue; |
1072 | debugf0("Removing dev %02x:%02x.%d\n", | 1070 | edac_dbg(0, "Removing dev %02x:%02x.%d\n", |
1073 | pdev->bus->number, | 1071 | pdev->bus->number, |
1074 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | 1072 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); |
1075 | pci_dev_put(pdev); | 1073 | pci_dev_put(pdev); |
1076 | } | 1074 | } |
1077 | } | 1075 | } |
@@ -1177,10 +1175,9 @@ static int sbridge_get_onedevice(struct pci_dev **prev, | |||
1177 | return -ENODEV; | 1175 | return -ENODEV; |
1178 | } | 1176 | } |
1179 | 1177 | ||
1180 | debugf0("Detected dev %02x:%d.%d PCI ID %04x:%04x\n", | 1178 | edac_dbg(0, "Detected dev %02x:%d.%d PCI ID %04x:%04x\n", |
1181 | bus, dev_descr->dev, | 1179 | bus, dev_descr->dev, dev_descr->func, |
1182 | dev_descr->func, | 1180 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
1183 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | ||
1184 | 1181 | ||
1185 | /* | 1182 | /* |
1186 | * As stated on drivers/pci/search.c, the reference count for | 1183 | * As stated on drivers/pci/search.c, the reference count for |
@@ -1297,10 +1294,10 @@ static int mci_bind_devs(struct mem_ctl_info *mci, | |||
1297 | goto error; | 1294 | goto error; |
1298 | } | 1295 | } |
1299 | 1296 | ||
1300 | debugf0("Associated PCI %02x.%02d.%d with dev = %p\n", | 1297 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", |
1301 | sbridge_dev->bus, | 1298 | sbridge_dev->bus, |
1302 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | 1299 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
1303 | pdev); | 1300 | pdev); |
1304 | } | 1301 | } |
1305 | 1302 | ||
1306 | /* Check if everything were registered */ | 1303 | /* Check if everything were registered */ |
@@ -1435,8 +1432,7 @@ static void sbridge_mce_output_error(struct mem_ctl_info *mci, | |||
1435 | * to the group of dimm's where the error may be happening. | 1432 | * to the group of dimm's where the error may be happening. |
1436 | */ | 1433 | */ |
1437 | snprintf(msg, sizeof(msg), | 1434 | snprintf(msg, sizeof(msg), |
1438 | "count:%d%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d", | 1435 | "%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d", |
1439 | core_err_cnt, | ||
1440 | overflow ? " OVERFLOW" : "", | 1436 | overflow ? " OVERFLOW" : "", |
1441 | (uncorrected_error && recoverable) ? " recoverable" : "", | 1437 | (uncorrected_error && recoverable) ? " recoverable" : "", |
1442 | area_type, | 1438 | area_type, |
@@ -1445,20 +1441,20 @@ static void sbridge_mce_output_error(struct mem_ctl_info *mci, | |||
1445 | channel_mask, | 1441 | channel_mask, |
1446 | rank); | 1442 | rank); |
1447 | 1443 | ||
1448 | debugf0("%s", msg); | 1444 | edac_dbg(0, "%s\n", msg); |
1449 | 1445 | ||
1450 | /* FIXME: need support for channel mask */ | 1446 | /* FIXME: need support for channel mask */ |
1451 | 1447 | ||
1452 | /* Call the helper to output message */ | 1448 | /* Call the helper to output message */ |
1453 | edac_mc_handle_error(tp_event, mci, | 1449 | edac_mc_handle_error(tp_event, mci, core_err_cnt, |
1454 | m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, | 1450 | m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, |
1455 | channel, dimm, -1, | 1451 | channel, dimm, -1, |
1456 | optype, msg, m); | 1452 | optype, msg); |
1457 | return; | 1453 | return; |
1458 | err_parsing: | 1454 | err_parsing: |
1459 | edac_mc_handle_error(tp_event, mci, 0, 0, 0, | 1455 | edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0, |
1460 | -1, -1, -1, | 1456 | -1, -1, -1, |
1461 | msg, "", m); | 1457 | msg, ""); |
1462 | 1458 | ||
1463 | } | 1459 | } |
1464 | 1460 | ||
@@ -1592,8 +1588,7 @@ static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) | |||
1592 | struct sbridge_pvt *pvt; | 1588 | struct sbridge_pvt *pvt; |
1593 | 1589 | ||
1594 | if (unlikely(!mci || !mci->pvt_info)) { | 1590 | if (unlikely(!mci || !mci->pvt_info)) { |
1595 | debugf0("MC: " __FILE__ ": %s(): dev = %p\n", | 1591 | edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); |
1596 | __func__, &sbridge_dev->pdev[0]->dev); | ||
1597 | 1592 | ||
1598 | sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); | 1593 | sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); |
1599 | return; | 1594 | return; |
@@ -1601,13 +1596,13 @@ static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) | |||
1601 | 1596 | ||
1602 | pvt = mci->pvt_info; | 1597 | pvt = mci->pvt_info; |
1603 | 1598 | ||
1604 | debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n", | 1599 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
1605 | __func__, mci, &sbridge_dev->pdev[0]->dev); | 1600 | mci, &sbridge_dev->pdev[0]->dev); |
1606 | 1601 | ||
1607 | /* Remove MC sysfs nodes */ | 1602 | /* Remove MC sysfs nodes */ |
1608 | edac_mc_del_mc(mci->dev); | 1603 | edac_mc_del_mc(mci->pdev); |
1609 | 1604 | ||
1610 | debugf1("%s: free mci struct\n", mci->ctl_name); | 1605 | edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); |
1611 | kfree(mci->ctl_name); | 1606 | kfree(mci->ctl_name); |
1612 | edac_mc_free(mci); | 1607 | edac_mc_free(mci); |
1613 | sbridge_dev->mci = NULL; | 1608 | sbridge_dev->mci = NULL; |
@@ -1638,8 +1633,8 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev) | |||
1638 | if (unlikely(!mci)) | 1633 | if (unlikely(!mci)) |
1639 | return -ENOMEM; | 1634 | return -ENOMEM; |
1640 | 1635 | ||
1641 | debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n", | 1636 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
1642 | __func__, mci, &sbridge_dev->pdev[0]->dev); | 1637 | mci, &sbridge_dev->pdev[0]->dev); |
1643 | 1638 | ||
1644 | pvt = mci->pvt_info; | 1639 | pvt = mci->pvt_info; |
1645 | memset(pvt, 0, sizeof(*pvt)); | 1640 | memset(pvt, 0, sizeof(*pvt)); |
@@ -1670,12 +1665,11 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev) | |||
1670 | get_memory_layout(mci); | 1665 | get_memory_layout(mci); |
1671 | 1666 | ||
1672 | /* record ptr to the generic device */ | 1667 | /* record ptr to the generic device */ |
1673 | mci->dev = &sbridge_dev->pdev[0]->dev; | 1668 | mci->pdev = &sbridge_dev->pdev[0]->dev; |
1674 | 1669 | ||
1675 | /* add this new MC control structure to EDAC's list of MCs */ | 1670 | /* add this new MC control structure to EDAC's list of MCs */ |
1676 | if (unlikely(edac_mc_add_mc(mci))) { | 1671 | if (unlikely(edac_mc_add_mc(mci))) { |
1677 | debugf0("MC: " __FILE__ | 1672 | edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); |
1678 | ": %s(): failed edac_mc_add_mc()\n", __func__); | ||
1679 | rc = -EINVAL; | 1673 | rc = -EINVAL; |
1680 | goto fail0; | 1674 | goto fail0; |
1681 | } | 1675 | } |
@@ -1722,7 +1716,8 @@ static int __devinit sbridge_probe(struct pci_dev *pdev, | |||
1722 | mc = 0; | 1716 | mc = 0; |
1723 | 1717 | ||
1724 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | 1718 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { |
1725 | debugf0("Registering MC#%d (%d of %d)\n", mc, mc + 1, num_mc); | 1719 | edac_dbg(0, "Registering MC#%d (%d of %d)\n", |
1720 | mc, mc + 1, num_mc); | ||
1726 | sbridge_dev->mc = mc++; | 1721 | sbridge_dev->mc = mc++; |
1727 | rc = sbridge_register_mci(sbridge_dev); | 1722 | rc = sbridge_register_mci(sbridge_dev); |
1728 | if (unlikely(rc < 0)) | 1723 | if (unlikely(rc < 0)) |
@@ -1752,7 +1747,7 @@ static void __devexit sbridge_remove(struct pci_dev *pdev) | |||
1752 | { | 1747 | { |
1753 | struct sbridge_dev *sbridge_dev; | 1748 | struct sbridge_dev *sbridge_dev; |
1754 | 1749 | ||
1755 | debugf0(__FILE__ ": %s()\n", __func__); | 1750 | edac_dbg(0, "\n"); |
1756 | 1751 | ||
1757 | /* | 1752 | /* |
1758 | * we have a trouble here: pdev value for removal will be wrong, since | 1753 | * we have a trouble here: pdev value for removal will be wrong, since |
@@ -1801,7 +1796,7 @@ static int __init sbridge_init(void) | |||
1801 | { | 1796 | { |
1802 | int pci_rc; | 1797 | int pci_rc; |
1803 | 1798 | ||
1804 | debugf2("MC: " __FILE__ ": %s()\n", __func__); | 1799 | edac_dbg(2, "\n"); |
1805 | 1800 | ||
1806 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ | 1801 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
1807 | opstate_init(); | 1802 | opstate_init(); |
@@ -1825,7 +1820,7 @@ static int __init sbridge_init(void) | |||
1825 | */ | 1820 | */ |
1826 | static void __exit sbridge_exit(void) | 1821 | static void __exit sbridge_exit(void) |
1827 | { | 1822 | { |
1828 | debugf2("MC: " __FILE__ ": %s()\n", __func__); | 1823 | edac_dbg(2, "\n"); |
1829 | pci_unregister_driver(&sbridge_driver); | 1824 | pci_unregister_driver(&sbridge_driver); |
1830 | mce_unregister_decode_chain(&sbridge_mce_dec); | 1825 | mce_unregister_decode_chain(&sbridge_mce_dec); |
1831 | } | 1826 | } |