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authorMauro Carvalho Chehab <mchehab@redhat.com>2012-01-28 07:09:38 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-05-28 18:10:58 -0400
commita895bf8b1e1ea4c032a8fa8a09475a2ce09fe77a (patch)
tree79a1110d0f4a6f2d50d870fa77d11a5311fee4fc /drivers/edac/sb_edac.c
parent5e2af0c09e60d11dd8297e259a9ca2b3d92d2cf4 (diff)
edac: move nr_pages to dimm struct
The number of pages is a dimm property. Move it to the dimm struct. After this change, it is possible to add sysfs nodes for the DIMM's that will properly represent the DIMM stick properties, including its size. A TODO fix here is to properly represent dual-rank/quad-rank DIMMs when the memory controller represents the memory via chip select rows. Reviewed-by: Aristeu Rozanski <arozansk@redhat.com> Acked-by: Borislav Petkov <borislav.petkov@amd.com> Acked-by: Chris Metcalf <cmetcalf@tilera.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Mark Gross <mark.gross@intel.com> Cc: Jason Uhlenkott <juhlenko@akamai.com> Cc: Tim Small <tim@buttersideup.com> Cc: Ranganathan Desikan <ravi@jetztechnologies.com> Cc: "Arvind R." <arvino55@gmail.com> Cc: Olof Johansson <olof@lixom.net> Cc: Egor Martovetsky <egor@pasemi.com> Cc: Michal Marek <mmarek@suse.cz> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Joe Perches <joe@perches.com> Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Hitoshi Mitake <h.mitake@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Josh Boyer <jwboyer@gmail.com> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/edac/sb_edac.c')
-rw-r--r--drivers/edac/sb_edac.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index d5892c052bf4..2ce9bf5e354b 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -561,7 +561,6 @@ static int get_dimm_config(struct mem_ctl_info *mci)
561 u32 reg; 561 u32 reg;
562 enum edac_type mode; 562 enum edac_type mode;
563 enum mem_type mtype; 563 enum mem_type mtype;
564 struct dimm_info *dimm;
565 564
566 pci_read_config_dword(pvt->pci_br, SAD_TARGET, &reg); 565 pci_read_config_dword(pvt->pci_br, SAD_TARGET, &reg);
567 pvt->sbridge_dev->source_id = SOURCE_ID(reg); 566 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
@@ -613,11 +612,11 @@ static int get_dimm_config(struct mem_ctl_info *mci)
613 /* On all supported DDR3 DIMM types, there are 8 banks available */ 612 /* On all supported DDR3 DIMM types, there are 8 banks available */
614 banks = 8; 613 banks = 8;
615 614
616 dimm = mci->dimms;
617 for (i = 0; i < NUM_CHANNELS; i++) { 615 for (i = 0; i < NUM_CHANNELS; i++) {
618 u32 mtr; 616 u32 mtr;
619 617
620 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) { 618 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
619 struct dimm_info *dimm = &mci->dimms[j];
621 pci_read_config_dword(pvt->pci_tad[i], 620 pci_read_config_dword(pvt->pci_tad[i],
622 mtr_regs[j], &mtr); 621 mtr_regs[j], &mtr);
623 debugf4("Channel #%d MTR%d = %x\n", i, j, mtr); 622 debugf4("Channel #%d MTR%d = %x\n", i, j, mtr);
@@ -642,15 +641,12 @@ static int get_dimm_config(struct mem_ctl_info *mci)
642 * csrows. 641 * csrows.
643 */ 642 */
644 csr = &mci->csrows[csrow]; 643 csr = &mci->csrows[csrow];
645 csr->nr_pages = npages;
646 csr->csrow_idx = csrow;
647 csr->nr_channels = 1;
648 csr->channels[0].chan_idx = i;
649 pvt->csrow_map[i][j] = csrow; 644 pvt->csrow_map[i][j] = csrow;
650 last_page += npages; 645 last_page += npages;
651 csrow++; 646 csrow++;
652 647
653 csr->channels[0].dimm = dimm; 648 csr->channels[0].dimm = dimm;
649 dimm->nr_pages = npages;
654 dimm->grain = 32; 650 dimm->grain = 32;
655 dimm->dtype = (banks == 8) ? DEV_X8 : DEV_X4; 651 dimm->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
656 dimm->mtype = mtype; 652 dimm->mtype = mtype;