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authorMauro Carvalho Chehab <mchehab@redhat.com>2012-04-16 14:10:55 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-05-28 18:13:44 -0400
commit705213580b82090c1f4277d7d8fbee898d53895e (patch)
tree2d2b388f93628e22a67aaf906cc08974d69f1302 /drivers/edac/i82975x_edac.c
parent0a8a9ac9ca24536416eea3b94a7d83f31676adc9 (diff)
i82975x_edac: convert driver to use the new edac ABI
The legacy edac ABI is going to be removed. Port the driver to use and benefit from the new API functionality. Cc: Ranganathan Desikan <ravi@jetztechnologies.com> Cc: "Arvind R." <arvino55@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/edac/i82975x_edac.c')
-rw-r--r--drivers/edac/i82975x_edac.c27
1 files changed, 20 insertions, 7 deletions
diff --git a/drivers/edac/i82975x_edac.c b/drivers/edac/i82975x_edac.c
index 014a9483fccc..092fa5ab2e1a 100644
--- a/drivers/edac/i82975x_edac.c
+++ b/drivers/edac/i82975x_edac.c
@@ -29,7 +29,8 @@
29#define PCI_DEVICE_ID_INTEL_82975_0 0x277c 29#define PCI_DEVICE_ID_INTEL_82975_0 0x277c
30#endif /* PCI_DEVICE_ID_INTEL_82975_0 */ 30#endif /* PCI_DEVICE_ID_INTEL_82975_0 */
31 31
32#define I82975X_NR_CSROWS(nr_chans) (8/(nr_chans)) 32#define I82975X_NR_DIMMS 8
33#define I82975X_NR_CSROWS(nr_chans) (I82975X_NR_DIMMS / (nr_chans))
33 34
34/* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */ 35/* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
35#define I82975X_EAP 0x58 /* Dram Error Address Pointer (32b) 36#define I82975X_EAP 0x58 /* Dram Error Address Pointer (32b)
@@ -287,7 +288,8 @@ static int i82975x_process_error_info(struct mem_ctl_info *mci,
287 return 1; 288 return 1;
288 289
289 if ((info->errsts ^ info->errsts2) & 0x0003) { 290 if ((info->errsts ^ info->errsts2) & 0x0003) {
290 edac_mc_handle_ce_no_info(mci, "UE overwrote CE"); 291 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0,
292 -1, -1, -1, "UE overwrote CE", "", NULL);
291 info->errsts = info->errsts2; 293 info->errsts = info->errsts2;
292 } 294 }
293 295
@@ -312,10 +314,15 @@ static int i82975x_process_error_info(struct mem_ctl_info *mci,
312 (1 << mci->csrows[row].channels[chan].dimm->grain)); 314 (1 << mci->csrows[row].channels[chan].dimm->grain));
313 315
314 if (info->errsts & 0x0002) 316 if (info->errsts & 0x0002)
315 edac_mc_handle_ue(mci, page, offst , row, "i82975x UE"); 317 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
318 page, offst, 0,
319 row, -1, -1,
320 "i82975x UE", "", NULL);
316 else 321 else
317 edac_mc_handle_ce(mci, page, offst, info->derrsyn, row, 322 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
318 chan, "i82975x CE"); 323 page, offst, info->derrsyn,
324 row, chan ? chan : 0, -1,
325 "i82975x CE", "", NULL);
319 326
320 return 1; 327 return 1;
321} 328}
@@ -473,6 +480,7 @@ static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
473{ 480{
474 int rc = -ENODEV; 481 int rc = -ENODEV;
475 struct mem_ctl_info *mci; 482 struct mem_ctl_info *mci;
483 struct edac_mc_layer layers[2];
476 struct i82975x_pvt *pvt; 484 struct i82975x_pvt *pvt;
477 void __iomem *mch_window; 485 void __iomem *mch_window;
478 u32 mchbar; 486 u32 mchbar;
@@ -541,8 +549,13 @@ static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
541 chans = dual_channel_active(mch_window) + 1; 549 chans = dual_channel_active(mch_window) + 1;
542 550
543 /* assuming only one controller, index thus is 0 */ 551 /* assuming only one controller, index thus is 0 */
544 mci = edac_mc_alloc(sizeof(*pvt), I82975X_NR_CSROWS(chans), 552 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
545 chans, 0); 553 layers[0].size = I82975X_NR_DIMMS;
554 layers[0].is_virt_csrow = true;
555 layers[1].type = EDAC_MC_LAYER_CHANNEL;
556 layers[1].size = I82975X_NR_CSROWS(chans);
557 layers[1].is_virt_csrow = false;
558 mci = new_edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
546 if (!mci) { 559 if (!mci) {
547 rc = -ENOMEM; 560 rc = -ENOMEM;
548 goto fail1; 561 goto fail1;