Merge branch 'x86/trampoline' into x86/urgent

x86/trampoline contains an urgent commit which is necessarily on a
newer baseline.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>

1 files changed, 25 insertions, 16 deletions

diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c
index 3bf2b2f490e7..52072c28a8a6 100644
--- a/drivers/edac/i82443bxgx_edac.c
+++ b/drivers/edac/i82443bxgx_edac.c
@@ -12,7 +12,7 @@
  * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
  *
  * Written with reference to 82443BX Host Bridge Datasheet:
- * http://download.intel.com/design/chipsets/datashts/29063301.pdf 
+ * http://download.intel.com/design/chipsets/datashts/29063301.pdf
  * references to this document given in [].
  *
  * This module doesn't support the 440LX, but it may be possible to
@@ -156,19 +156,19 @@ static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
         if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
                 error_found = 1;
                 if (handle_errors)
-                        edac_mc_handle_ce(mci, page, pageoffset,
-                                /* 440BX/GX don't make syndrome information
-                                 * available */
-                                0, edac_mc_find_csrow_by_page(mci, page), 0,
-                                mci->ctl_name);
+                        edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
+                                             page, pageoffset, 0,
+                                             edac_mc_find_csrow_by_page(mci, page),
+                                             0, -1, mci->ctl_name, "", NULL);
         }
 
         if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
                 error_found = 1;
                 if (handle_errors)
-                        edac_mc_handle_ue(mci, page, pageoffset,
-                                        edac_mc_find_csrow_by_page(mci, page),
-                                        mci->ctl_name);
+                        edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
+                                             page, pageoffset, 0,
+                                             edac_mc_find_csrow_by_page(mci, page),
+                                             0, -1, mci->ctl_name, "", NULL);
         }
 
         return error_found;
@@ -189,6 +189,7 @@ static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
                                 enum mem_type mtype)
 {
         struct csrow_info *csrow;
+        struct dimm_info *dimm;
         int index;
         u8 drbar, dramc;
         u32 row_base, row_high_limit, row_high_limit_last;
@@ -197,6 +198,8 @@ static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
         row_high_limit_last = 0;
         for (index = 0; index < mci->nr_csrows; index++) {
                 csrow = &mci->csrows[index];
+                dimm = csrow->channels[0].dimm;
+
                 pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
                 debugf1("MC%d: %s: %s() Row=%d DRB = %#0x\n",
                         mci->mc_idx, __FILE__, __func__, index, drbar);
@@ -217,14 +220,14 @@ static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
                 row_base = row_high_limit_last;
                 csrow->first_page = row_base >> PAGE_SHIFT;
                 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
-                csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
+                dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
                 /* EAP reports in 4kilobyte granularity [61] */
-                csrow->grain = 1 << 12;
-                csrow->mtype = mtype;
+                dimm->grain = 1 << 12;
+                dimm->mtype = mtype;
                 /* I don't think 440BX can tell you device type? FIXME? */
-                csrow->dtype = DEV_UNKNOWN;
+                dimm->dtype = DEV_UNKNOWN;
                 /* Mode is global to all rows on 440BX */
-                csrow->edac_mode = edac_mode;
+                dimm->edac_mode = edac_mode;
                 row_high_limit_last = row_high_limit;
         }
 }
@@ -232,6 +235,7 @@ static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
 static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
 {
         struct mem_ctl_info *mci;
+        struct edac_mc_layer layers[2];
         u8 dramc;
         u32 nbxcfg, ecc_mode;
         enum mem_type mtype;
@@ -245,8 +249,13 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
         if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
                 return -EIO;
 
-        mci = edac_mc_alloc(0, I82443BXGX_NR_CSROWS, I82443BXGX_NR_CHANS, 0);
-
+        layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
+        layers[0].size = I82443BXGX_NR_CSROWS;
+        layers[0].is_virt_csrow = true;
+        layers[1].type = EDAC_MC_LAYER_CHANNEL;
+        layers[1].size = I82443BXGX_NR_CHANS;
+        layers[1].is_virt_csrow = false;
+        mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
         if (mci == NULL)
                 return -ENOMEM;