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authorMauro Carvalho Chehab <mchehab@redhat.com>2010-08-26 19:58:45 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2010-08-30 13:56:43 -0400
commitaf3d8831e7e2036cd453c852d206b892b19c8820 (patch)
tree8960442e2a41d2d6421f3949efaeee581997d03f /drivers/edac/i7300_edac.c
parentfcaf780b2ad352edaeb1d1c07a6da053266b1eed (diff)
i7300_edac: display info if ECC is enabled or not
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/edac/i7300_edac.c')
-rw-r--r--drivers/edac/i7300_edac.c28
1 files changed, 20 insertions, 8 deletions
diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c
index eb3f30e96ee3..db194b6b3e42 100644
--- a/drivers/edac/i7300_edac.c
+++ b/drivers/edac/i7300_edac.c
@@ -80,17 +80,19 @@
80 */ 80 */
81 81
82 /* OFFSETS for Function 0 */ 82 /* OFFSETS for Function 0 */
83#define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */ 83#define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */
84#define MAXCH 0x56 /* Max Channel Number */ 84#define MAXCH 0x56 /* Max Channel Number */
85#define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */ 85#define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */
86 86
87 /* OFFSETS for Function 1 */ 87 /* OFFSETS for Function 1 */
88#define TOLM 0x6C 88#define MC_SETTINGS 0x40
89#define REDMEMB 0x7C
90 89
91#define MIR0 0x80 90#define TOLM 0x6C
92#define MIR1 0x84 91#define REDMEMB 0x7C
93#define MIR2 0x88 92
93#define MIR0 0x80
94#define MIR1 0x84
95#define MIR2 0x88
94 96
95#if 0 97#if 0
96#define AMIR0 0x8c 98#define AMIR0 0x8c
@@ -393,6 +395,7 @@ struct i7300_pvt {
393 395
394 u16 tolm; /* top of low memory */ 396 u16 tolm; /* top of low memory */
395 u64 ambase; /* AMB BAR */ 397 u64 ambase; /* AMB BAR */
398 u32 mc_settings;
396 399
397 u16 mir[MAX_MIR]; 400 u16 mir[MAX_MIR];
398 401
@@ -1020,6 +1023,15 @@ static int i7300_get_mc_regs(struct mem_ctl_info *mci)
1020 debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n", 1023 debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
1021 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); 1024 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
1022 1025
1026 /* Get memory controller settings */
1027 pci_read_config_dword(pvt->branchmap_werrors, MC_SETTINGS,
1028 &pvt->mc_settings);
1029 debugf0("Memory controller operating on %s mode\n",
1030 pvt->mc_settings & (1 << 16)? "mirrored" : "non-mirrored");
1031 debugf0("Error detection is %s\n",
1032 pvt->mc_settings & (1 << 5)? "enabled" : "disabled");
1033
1034 /* Get Memory Interleave Range registers */
1023 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir[0]); 1035 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir[0]);
1024 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir[1]); 1036 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir[1]);
1025 pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir[2]); 1037 pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir[2]);