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authorBorislav Petkov <borislav.petkov@amd.com>2009-07-28 08:14:24 -0400
committerBorislav Petkov <borislav.petkov@amd.com>2009-09-14 13:01:30 -0400
commit56cad2d6fb832a876ab8bda4b01e5d0722dc754b (patch)
treea6861ac9a9f4aeae8a440b810dbaabd48a0ea06e /drivers/edac/edac_mce_amd.c
parentab5535e70fb35b8046b6ace50259fe212e074a4f (diff)
EDAC, AMD: decode bus unit MCEs
... according to Table 69, Fam10h BKDG (31116, rev. 3.28). Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac/edac_mce_amd.c')
-rw-r--r--drivers/edac/edac_mce_amd.c46
1 files changed, 46 insertions, 0 deletions
diff --git a/drivers/edac/edac_mce_amd.c b/drivers/edac/edac_mce_amd.c
index b30a8306b143..e1f32c36248d 100644
--- a/drivers/edac/edac_mce_amd.c
+++ b/drivers/edac/edac_mce_amd.c
@@ -228,6 +228,48 @@ wrong_ic_mce:
228 pr_warning("Corrupted IC MCE info?\n"); 228 pr_warning("Corrupted IC MCE info?\n");
229} 229}
230 230
231static void amd_decode_bu_mce(u64 mc2_status)
232{
233 u32 ec = mc2_status & 0xffff;
234 u32 xec = (mc2_status >> 16) & 0xf;
235
236 pr_emerg(" Bus Unit Error");
237
238 if (xec == 0x1)
239 pr_cont(" in the write data buffers.\n");
240 else if (xec == 0x3)
241 pr_cont(" in the victim data buffers.\n");
242 else if (xec == 0x2 && MEM_ERROR(ec))
243 pr_cont(": %s error in the L2 cache tags.\n", RRRR_MSG(ec));
244 else if (xec == 0x0) {
245 if (TLB_ERROR(ec))
246 pr_cont(": %s error in a Page Descriptor Cache or "
247 "Guest TLB.\n", TT_MSG(ec));
248 else if (BUS_ERROR(ec))
249 pr_cont(": %s/ECC error in data read from NB: %s.\n",
250 RRRR_MSG(ec), PP_MSG(ec));
251 else if (MEM_ERROR(ec)) {
252 u8 rrrr = (ec >> 4) & 0xf;
253
254 if (rrrr >= 0x7)
255 pr_cont(": %s error during data copyback.\n",
256 RRRR_MSG(ec));
257 else if (rrrr <= 0x1)
258 pr_cont(": %s parity/ECC error during data "
259 "access from L2.\n", RRRR_MSG(ec));
260 else
261 goto wrong_bu_mce;
262 } else
263 goto wrong_bu_mce;
264 } else
265 goto wrong_bu_mce;
266
267 return;
268
269wrong_bu_mce:
270 pr_warning("Corrupted BU MCE info?\n");
271}
272
231void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors) 273void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
232{ 274{
233 u32 ec = ERROR_CODE(regs->nbsl); 275 u32 ec = ERROR_CODE(regs->nbsl);
@@ -320,6 +362,10 @@ void decode_mce(struct mce *m)
320 amd_decode_ic_mce(m->status); 362 amd_decode_ic_mce(m->status);
321 break; 363 break;
322 364
365 case 2:
366 amd_decode_bu_mce(m->status);
367 break;
368
323 case 4: 369 case 4:
324 regs.nbsl = (u32) m->status; 370 regs.nbsl = (u32) m->status;
325 regs.nbsh = (u32)(m->status >> 32); 371 regs.nbsh = (u32)(m->status >> 32);