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authorAlan Cox <alan@lxorguk.ukuu.org.uk>2006-01-18 20:44:08 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-01-18 22:20:31 -0500
commit806c35f5057a64d3061ee4e2b1023bf6f6d328e2 (patch)
tree89bc8ffd498475ca04a2760dabfd882e9de5e8b1 /drivers/edac/amd76x_edac.c
parent715b49ef2de6fcead0776d9349071670282faf65 (diff)
[PATCH] EDAC: drivers for AMD 76x and Intel E750x, E752x
Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/edac/amd76x_edac.c')
-rw-r--r--drivers/edac/amd76x_edac.c356
1 files changed, 356 insertions, 0 deletions
diff --git a/drivers/edac/amd76x_edac.c b/drivers/edac/amd76x_edac.c
new file mode 100644
index 000000000000..8e2b1295e70c
--- /dev/null
+++ b/drivers/edac/amd76x_edac.c
@@ -0,0 +1,356 @@
1/*
2 * AMD 76x Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Thayne Harbaugh
8 * Based on work by Dan Hollis <goemon at anime dot net> and others.
9 * http://www.anime.net/~goemon/linux-ecc/
10 *
11 * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
12 *
13 */
14
15
16#include <linux/config.h>
17#include <linux/module.h>
18#include <linux/init.h>
19
20#include <linux/pci.h>
21#include <linux/pci_ids.h>
22
23#include <linux/slab.h>
24
25#include "edac_mc.h"
26
27
28#define AMD76X_NR_CSROWS 8
29#define AMD76X_NR_CHANS 1
30#define AMD76X_NR_DIMMS 4
31
32
33/* AMD 76x register addresses - device 0 function 0 - PCI bridge */
34#define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b)
35 *
36 * 31:16 reserved
37 * 15:14 SERR enabled: x1=ue 1x=ce
38 * 13 reserved
39 * 12 diag: disabled, enabled
40 * 11:10 mode: dis, EC, ECC, ECC+scrub
41 * 9:8 status: x1=ue 1x=ce
42 * 7:4 UE cs row
43 * 3:0 CE cs row
44 */
45#define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b)
46 *
47 * 31:26 clock disable 5 - 0
48 * 25 SDRAM init
49 * 24 reserved
50 * 23 mode register service
51 * 22:21 suspend to RAM
52 * 20 burst refresh enable
53 * 19 refresh disable
54 * 18 reserved
55 * 17:16 cycles-per-refresh
56 * 15:8 reserved
57 * 7:0 x4 mode enable 7 - 0
58 */
59#define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b)
60 *
61 * 31:23 chip-select base
62 * 22:16 reserved
63 * 15:7 chip-select mask
64 * 6:3 reserved
65 * 2:1 address mode
66 * 0 chip-select enable
67 */
68
69
70struct amd76x_error_info {
71 u32 ecc_mode_status;
72};
73
74
75enum amd76x_chips {
76 AMD761 = 0,
77 AMD762
78};
79
80
81struct amd76x_dev_info {
82 const char *ctl_name;
83};
84
85
86static const struct amd76x_dev_info amd76x_devs[] = {
87 [AMD761] = {.ctl_name = "AMD761"},
88 [AMD762] = {.ctl_name = "AMD762"},
89};
90
91
92/**
93 * amd76x_get_error_info - fetch error information
94 * @mci: Memory controller
95 * @info: Info to fill in
96 *
97 * Fetch and store the AMD76x ECC status. Clear pending status
98 * on the chip so that further errors will be reported
99 */
100
101static void amd76x_get_error_info (struct mem_ctl_info *mci,
102 struct amd76x_error_info *info)
103{
104 pci_read_config_dword(mci->pdev, AMD76X_ECC_MODE_STATUS,
105 &info->ecc_mode_status);
106
107 if (info->ecc_mode_status & BIT(8))
108 pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
109 (u32) BIT(8), (u32) BIT(8));
110
111 if (info->ecc_mode_status & BIT(9))
112 pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
113 (u32) BIT(9), (u32) BIT(9));
114}
115
116
117/**
118 * amd76x_process_error_info - Error check
119 * @mci: Memory controller
120 * @info: Previously fetched information from chip
121 * @handle_errors: 1 if we should do recovery
122 *
123 * Process the chip state and decide if an error has occurred.
124 * A return of 1 indicates an error. Also if handle_errors is true
125 * then attempt to handle and clean up after the error
126 */
127
128static int amd76x_process_error_info (struct mem_ctl_info *mci,
129 struct amd76x_error_info *info, int handle_errors)
130{
131 int error_found;
132 u32 row;
133
134 error_found = 0;
135
136 /*
137 * Check for an uncorrectable error
138 */
139 if (info->ecc_mode_status & BIT(8)) {
140 error_found = 1;
141
142 if (handle_errors) {
143 row = (info->ecc_mode_status >> 4) & 0xf;
144 edac_mc_handle_ue(mci,
145 mci->csrows[row].first_page, 0, row,
146 mci->ctl_name);
147 }
148 }
149
150 /*
151 * Check for a correctable error
152 */
153 if (info->ecc_mode_status & BIT(9)) {
154 error_found = 1;
155
156 if (handle_errors) {
157 row = info->ecc_mode_status & 0xf;
158 edac_mc_handle_ce(mci,
159 mci->csrows[row].first_page, 0, 0, row, 0,
160 mci->ctl_name);
161 }
162 }
163 return error_found;
164}
165
166/**
167 * amd76x_check - Poll the controller
168 * @mci: Memory controller
169 *
170 * Called by the poll handlers this function reads the status
171 * from the controller and checks for errors.
172 */
173
174static void amd76x_check(struct mem_ctl_info *mci)
175{
176 struct amd76x_error_info info;
177 debugf3("MC: " __FILE__ ": %s()\n", __func__);
178 amd76x_get_error_info(mci, &info);
179 amd76x_process_error_info(mci, &info, 1);
180}
181
182
183/**
184 * amd76x_probe1 - Perform set up for detected device
185 * @pdev; PCI device detected
186 * @dev_idx: Device type index
187 *
188 * We have found an AMD76x and now need to set up the memory
189 * controller status reporting. We configure and set up the
190 * memory controller reporting and claim the device.
191 */
192
193static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
194{
195 int rc = -ENODEV;
196 int index;
197 struct mem_ctl_info *mci = NULL;
198 enum edac_type ems_modes[] = {
199 EDAC_NONE,
200 EDAC_EC,
201 EDAC_SECDED,
202 EDAC_SECDED
203 };
204 u32 ems;
205 u32 ems_mode;
206
207 debugf0("MC: " __FILE__ ": %s()\n", __func__);
208
209 pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
210 ems_mode = (ems >> 10) & 0x3;
211
212 mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS);
213
214 if (mci == NULL) {
215 rc = -ENOMEM;
216 goto fail;
217 }
218
219 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
220
221 mci->pdev = pci_dev_get(pdev);
222 mci->mtype_cap = MEM_FLAG_RDDR;
223
224 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
225 mci->edac_cap = ems_mode ?
226 (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
227
228 mci->mod_name = BS_MOD_STR;
229 mci->mod_ver = "$Revision: 1.4.2.5 $";
230 mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
231 mci->edac_check = amd76x_check;
232 mci->ctl_page_to_phys = NULL;
233
234 for (index = 0; index < mci->nr_csrows; index++) {
235 struct csrow_info *csrow = &mci->csrows[index];
236 u32 mba;
237 u32 mba_base;
238 u32 mba_mask;
239 u32 dms;
240
241 /* find the DRAM Chip Select Base address and mask */
242 pci_read_config_dword(mci->pdev,
243 AMD76X_MEM_BASE_ADDR + (index * 4),
244 &mba);
245
246 if (!(mba & BIT(0)))
247 continue;
248
249 mba_base = mba & 0xff800000UL;
250 mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
251
252 pci_read_config_dword(mci->pdev, AMD76X_DRAM_MODE_STATUS,
253 &dms);
254
255 csrow->first_page = mba_base >> PAGE_SHIFT;
256 csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
257 csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
258 csrow->page_mask = mba_mask >> PAGE_SHIFT;
259 csrow->grain = csrow->nr_pages << PAGE_SHIFT;
260 csrow->mtype = MEM_RDDR;
261 csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
262 csrow->edac_mode = ems_modes[ems_mode];
263 }
264
265 /* clear counters */
266 pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS, (u32) (0x3 << 8),
267 (u32) (0x3 << 8));
268
269 if (edac_mc_add_mc(mci)) {
270 debugf3("MC: " __FILE__
271 ": %s(): failed edac_mc_add_mc()\n", __func__);
272 goto fail;
273 }
274
275 /* get this far and it's successful */
276 debugf3("MC: " __FILE__ ": %s(): success\n", __func__);
277 return 0;
278
279fail:
280 if (mci) {
281 if(mci->pdev)
282 pci_dev_put(mci->pdev);
283 edac_mc_free(mci);
284 }
285 return rc;
286}
287
288/* returns count (>= 0), or negative on error */
289static int __devinit amd76x_init_one(struct pci_dev *pdev,
290 const struct pci_device_id *ent)
291{
292 debugf0("MC: " __FILE__ ": %s()\n", __func__);
293
294 /* don't need to call pci_device_enable() */
295 return amd76x_probe1(pdev, ent->driver_data);
296}
297
298
299/**
300 * amd76x_remove_one - driver shutdown
301 * @pdev: PCI device being handed back
302 *
303 * Called when the driver is unloaded. Find the matching mci
304 * structure for the device then delete the mci and free the
305 * resources.
306 */
307
308static void __devexit amd76x_remove_one(struct pci_dev *pdev)
309{
310 struct mem_ctl_info *mci;
311
312 debugf0(__FILE__ ": %s()\n", __func__);
313
314 if ((mci = edac_mc_find_mci_by_pdev(pdev)) == NULL)
315 return;
316 if (edac_mc_del_mc(mci))
317 return;
318 pci_dev_put(mci->pdev);
319 edac_mc_free(mci);
320}
321
322
323static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = {
324 {PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
325 AMD762},
326 {PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
327 AMD761},
328 {0,} /* 0 terminated list. */
329};
330
331MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);
332
333
334static struct pci_driver amd76x_driver = {
335 .name = BS_MOD_STR,
336 .probe = amd76x_init_one,
337 .remove = __devexit_p(amd76x_remove_one),
338 .id_table = amd76x_pci_tbl,
339};
340
341int __init amd76x_init(void)
342{
343 return pci_register_driver(&amd76x_driver);
344}
345
346static void __exit amd76x_exit(void)
347{
348 pci_unregister_driver(&amd76x_driver);
349}
350
351module_init(amd76x_init);
352module_exit(amd76x_exit);
353
354MODULE_LICENSE("GPL");
355MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
356MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");