Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: (38 commits)
  amd64_edac: Fix decode_syndrome types
  amd64_edac: Fix DCT argument type
  amd64_edac: Fix ranges signedness
  amd64_edac: Drop local variable
  amd64_edac: Fix PCI config addressing types
  amd64_edac: Fix DRAM base macros
  amd64_edac: Fix node id signedness
  amd64_edac: Drop redundant declarations
  amd64_edac: Enable driver on F15h
  amd64_edac: Adjust ECC symbol size to F15h
  amd64_edac: Simplify scrubrate setting
  PCI: Rename CPU PCI id define
  amd64_edac: Improve DRAM address mapping
  amd64_edac: Sanitize ->read_dram_ctl_register
  amd64_edac: Adjust sys_addr to chip select conversion routine to F15h
  amd64_edac: Beef up early exit reporting
  amd64_edac: Revamp online spare handling
  amd64_edac: Fix channel interleave removal
  amd64_edac: Correct node interleaving removal
  amd64_edac: Add support for interleaved region swapping
  ...

Fix up trivial conflict in include/linux/pci_ids.h due to
AMD_15H_NB_MISC being renamed as AMD_15H_NB_F3 next to the new
AMD_15H_NB_LINK entry.

1 files changed, 4 insertions, 4 deletions

diff --git a/drivers/edac/amd64_edac_inj.c b/drivers/edac/amd64_edac_inj.c
index 688478de1cbd..303f10e03dda 100644
--- a/drivers/edac/amd64_edac_inj.c
+++ b/drivers/edac/amd64_edac_inj.c
@@ -117,13 +117,13 @@ static ssize_t amd64_inject_read_store(struct mem_ctl_info *mci,
                 /* Form value to choose 16-byte section of cacheline */
                 section = F10_NB_ARRAY_DRAM_ECC |
                                 SET_NB_ARRAY_ADDRESS(pvt->injection.section);
-                pci_write_config_dword(pvt->F3, F10_NB_ARRAY_ADDR, section);
+                amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
 
                 word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word,
                                                 pvt->injection.bit_map);
 
                 /* Issue 'word' and 'bit' along with the READ request */
-                pci_write_config_dword(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
+                amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
 
                 debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
 
@@ -150,13 +150,13 @@ static ssize_t amd64_inject_write_store(struct mem_ctl_info *mci,
                 /* Form value to choose 16-byte section of cacheline */
                 section = F10_NB_ARRAY_DRAM_ECC |
                                 SET_NB_ARRAY_ADDRESS(pvt->injection.section);
-                pci_write_config_dword(pvt->F3, F10_NB_ARRAY_ADDR, section);
+                amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
 
                 word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word,
                                                 pvt->injection.bit_map);
 
                 /* Issue 'word' and 'bit' along with the READ request */
-                pci_write_config_dword(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
+                amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
 
                 debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);