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authorBorislav Petkov <borislav.petkov@amd.com>2010-09-02 12:33:24 -0400
committerBorislav Petkov <bp@amd64.org>2010-10-21 08:47:59 -0400
commit9cdeb404a1870c5022915e576dbdc3cde21af5bf (patch)
tree19843bf914f56f362a7c9cdf86c27a648caa475c /drivers/edac/amd64_edac_dbg.c
parent30e1f7a8122145f44f45c95366e27b6bb0b08428 (diff)
EDAC, MCE: Rework MCE injection
Add sysfs injection facilities for testing of the MCE decoding code. Remove large parts of amd64_edac_dbg.c, as a result, which did only NB MCE injection anyway and the new injection code supports that functionality already. Add an injection module so that MCE decoding code in production kernels like those in RHEL and SLES can be tested. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac/amd64_edac_dbg.c')
-rw-r--r--drivers/edac/amd64_edac_dbg.c213
1 files changed, 12 insertions, 201 deletions
diff --git a/drivers/edac/amd64_edac_dbg.c b/drivers/edac/amd64_edac_dbg.c
index f6d5695de5b6..e3562288f4ce 100644
--- a/drivers/edac/amd64_edac_dbg.c
+++ b/drivers/edac/amd64_edac_dbg.c
@@ -1,173 +1,16 @@
1#include "amd64_edac.h" 1#include "amd64_edac.h"
2 2
3/* 3#define EDAC_DCT_ATTR_SHOW(reg) \
4 * accept a hex value and store it into the virtual error register file, field: 4static ssize_t amd64_##reg##_show(struct mem_ctl_info *mci, char *data) \
5 * nbeal and nbeah. Assume virtual error values have already been set for: NBSL, 5{ \
6 * NBSH and NBCFG. Then proceed to map the error values to a MC, CSROW and 6 struct amd64_pvt *pvt = mci->pvt_info; \
7 * CHANNEL 7 return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \
8 */
9static ssize_t amd64_nbea_store(struct mem_ctl_info *mci, const char *data,
10 size_t count)
11{
12 struct amd64_pvt *pvt = mci->pvt_info;
13 u64 value;
14 int ret = 0;
15 struct mce m;
16
17 ret = strict_strtoull(data, 16, &value);
18 if (ret != -EINVAL) {
19 struct err_regs *regs = &pvt->ctl_error_info;
20
21 debugf0("received NBEA= 0x%llx\n", value);
22
23 /* place the value into the virtual error packet */
24 pvt->ctl_error_info.nbeal = (u32) value;
25 value >>= 32;
26 pvt->ctl_error_info.nbeah = (u32) value;
27
28 m.addr = value;
29 m.status = regs->nbsl | ((u64)regs->nbsh << 32);
30
31 /* Process the Mapping request */
32 /* TODO: Add race prevention */
33 amd_decode_nb_mce(pvt->mc_node_id, &m, regs->nbcfg);
34
35 return count;
36 }
37 return ret;
38} 8}
39 9
40/* display back what the last NBEA (MCA NB Address (MC4_ADDR)) was written */ 10EDAC_DCT_ATTR_SHOW(dhar);
41static ssize_t amd64_nbea_show(struct mem_ctl_info *mci, char *data) 11EDAC_DCT_ATTR_SHOW(dbam0);
42{ 12EDAC_DCT_ATTR_SHOW(top_mem);
43 struct amd64_pvt *pvt = mci->pvt_info; 13EDAC_DCT_ATTR_SHOW(top_mem2);
44 u64 value;
45
46 value = pvt->ctl_error_info.nbeah;
47 value <<= 32;
48 value |= pvt->ctl_error_info.nbeal;
49
50 return sprintf(data, "%llx\n", value);
51}
52
53/* store the NBSL (MCA NB Status Low (MC4_STATUS)) value user desires */
54static ssize_t amd64_nbsl_store(struct mem_ctl_info *mci, const char *data,
55 size_t count)
56{
57 struct amd64_pvt *pvt = mci->pvt_info;
58 unsigned long value;
59 int ret = 0;
60
61 ret = strict_strtoul(data, 16, &value);
62 if (ret != -EINVAL) {
63 debugf0("received NBSL= 0x%lx\n", value);
64
65 pvt->ctl_error_info.nbsl = (u32) value;
66
67 return count;
68 }
69 return ret;
70}
71
72/* display back what the last NBSL value written */
73static ssize_t amd64_nbsl_show(struct mem_ctl_info *mci, char *data)
74{
75 struct amd64_pvt *pvt = mci->pvt_info;
76 u32 value;
77
78 value = pvt->ctl_error_info.nbsl;
79
80 return sprintf(data, "%x\n", value);
81}
82
83/* store the NBSH (MCA NB Status High) value user desires */
84static ssize_t amd64_nbsh_store(struct mem_ctl_info *mci, const char *data,
85 size_t count)
86{
87 struct amd64_pvt *pvt = mci->pvt_info;
88 unsigned long value;
89 int ret = 0;
90
91 ret = strict_strtoul(data, 16, &value);
92 if (ret != -EINVAL) {
93 debugf0("received NBSH= 0x%lx\n", value);
94
95 pvt->ctl_error_info.nbsh = (u32) value;
96
97 return count;
98 }
99 return ret;
100}
101
102/* display back what the last NBSH value written */
103static ssize_t amd64_nbsh_show(struct mem_ctl_info *mci, char *data)
104{
105 struct amd64_pvt *pvt = mci->pvt_info;
106 u32 value;
107
108 value = pvt->ctl_error_info.nbsh;
109
110 return sprintf(data, "%x\n", value);
111}
112
113/* accept and store the NBCFG (MCA NB Configuration) value user desires */
114static ssize_t amd64_nbcfg_store(struct mem_ctl_info *mci,
115 const char *data, size_t count)
116{
117 struct amd64_pvt *pvt = mci->pvt_info;
118 unsigned long value;
119 int ret = 0;
120
121 ret = strict_strtoul(data, 16, &value);
122 if (ret != -EINVAL) {
123 debugf0("received NBCFG= 0x%lx\n", value);
124
125 pvt->ctl_error_info.nbcfg = (u32) value;
126
127 return count;
128 }
129 return ret;
130}
131
132/* various show routines for the controls of a MCI */
133static ssize_t amd64_nbcfg_show(struct mem_ctl_info *mci, char *data)
134{
135 struct amd64_pvt *pvt = mci->pvt_info;
136
137 return sprintf(data, "%x\n", pvt->ctl_error_info.nbcfg);
138}
139
140
141static ssize_t amd64_dhar_show(struct mem_ctl_info *mci, char *data)
142{
143 struct amd64_pvt *pvt = mci->pvt_info;
144
145 return sprintf(data, "%x\n", pvt->dhar);
146}
147
148
149static ssize_t amd64_dbam_show(struct mem_ctl_info *mci, char *data)
150{
151 struct amd64_pvt *pvt = mci->pvt_info;
152
153 return sprintf(data, "%x\n", pvt->dbam0);
154}
155
156
157static ssize_t amd64_topmem_show(struct mem_ctl_info *mci, char *data)
158{
159 struct amd64_pvt *pvt = mci->pvt_info;
160
161 return sprintf(data, "%llx\n", pvt->top_mem);
162}
163
164
165static ssize_t amd64_topmem2_show(struct mem_ctl_info *mci, char *data)
166{
167 struct amd64_pvt *pvt = mci->pvt_info;
168
169 return sprintf(data, "%llx\n", pvt->top_mem2);
170}
171 14
172static ssize_t amd64_hole_show(struct mem_ctl_info *mci, char *data) 15static ssize_t amd64_hole_show(struct mem_ctl_info *mci, char *data)
173{ 16{
@@ -188,38 +31,6 @@ struct mcidev_sysfs_attribute amd64_dbg_attrs[] = {
188 31
189 { 32 {
190 .attr = { 33 .attr = {
191 .name = "nbea_ctl",
192 .mode = (S_IRUGO | S_IWUSR)
193 },
194 .show = amd64_nbea_show,
195 .store = amd64_nbea_store,
196 },
197 {
198 .attr = {
199 .name = "nbsl_ctl",
200 .mode = (S_IRUGO | S_IWUSR)
201 },
202 .show = amd64_nbsl_show,
203 .store = amd64_nbsl_store,
204 },
205 {
206 .attr = {
207 .name = "nbsh_ctl",
208 .mode = (S_IRUGO | S_IWUSR)
209 },
210 .show = amd64_nbsh_show,
211 .store = amd64_nbsh_store,
212 },
213 {
214 .attr = {
215 .name = "nbcfg_ctl",
216 .mode = (S_IRUGO | S_IWUSR)
217 },
218 .show = amd64_nbcfg_show,
219 .store = amd64_nbcfg_store,
220 },
221 {
222 .attr = {
223 .name = "dhar", 34 .name = "dhar",
224 .mode = (S_IRUGO) 35 .mode = (S_IRUGO)
225 }, 36 },
@@ -231,7 +42,7 @@ struct mcidev_sysfs_attribute amd64_dbg_attrs[] = {
231 .name = "dbam", 42 .name = "dbam",
232 .mode = (S_IRUGO) 43 .mode = (S_IRUGO)
233 }, 44 },
234 .show = amd64_dbam_show, 45 .show = amd64_dbam0_show,
235 .store = NULL, 46 .store = NULL,
236 }, 47 },
237 { 48 {
@@ -239,7 +50,7 @@ struct mcidev_sysfs_attribute amd64_dbg_attrs[] = {
239 .name = "topmem", 50 .name = "topmem",
240 .mode = (S_IRUGO) 51 .mode = (S_IRUGO)
241 }, 52 },
242 .show = amd64_topmem_show, 53 .show = amd64_top_mem_show,
243 .store = NULL, 54 .store = NULL,
244 }, 55 },
245 { 56 {
@@ -247,7 +58,7 @@ struct mcidev_sysfs_attribute amd64_dbg_attrs[] = {
247 .name = "topmem2", 58 .name = "topmem2",
248 .mode = (S_IRUGO) 59 .mode = (S_IRUGO)
249 }, 60 },
250 .show = amd64_topmem2_show, 61 .show = amd64_top_mem2_show,
251 .store = NULL, 62 .store = NULL,
252 }, 63 },
253 { 64 {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 07:15:21 -0500