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authorLinus Torvalds <torvalds@linux-foundation.org>2014-12-08 23:17:49 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-12-08 23:17:49 -0500
commit0160928e792eff243c84b39a46cddb2fb89da0cb (patch)
tree0d8f0b4c0a6218c1618771bed48af1695ee2a3be /drivers/edac/amd64_edac.h
parent3a7dbed7f23cdde8394e9adf92cc222856e0fc1e (diff)
parent50872ccd8786dc72bc5a32c17695561e031fae4c (diff)
Merge tag 'edac_for_3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
Pull EDAC updates from Borislav Petkov: "EDAC updates all over the place: - Enablement for AMD F15h models 0x60 CPUs. Most notably DDR4 RAM support. Out of tree stuff is adding the required PCI IDs. From Aravind Gopalakrishnan. - Enable amd64_edac for 32-bit due to popular demand. From Tomasz Pala. - Convert the AMD MCE injection module to debugfs, where it belongs. - Misc EDAC cleanups" * tag 'edac_for_3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: EDAC, MCE, AMD: Correct formatting of decoded text EDAC, mce_amd_inj: Add an injector function EDAC, mce_amd_inj: Add hw-injection attributes EDAC, mce_amd_inj: Enable direct writes to MCE MSRs EDAC, mce_amd_inj: Convert mce_amd_inj module to debugfs EDAC: Delete unnecessary check before calling pci_dev_put() EDAC, pci_sysfs: remove unneccessary ifdef around entire file ghes_edac: Use snprintf() to silence a static checker warning amd64_edac: Build module on x86-32 EDAC, MCE, AMD: Add decoding table for MC6 xec amd64_edac: Add F15h M60h support {mv64x60,ppc4xx}_edac,: Remove deprecated IRQF_DISABLED EDAC: Sync memory types and names EDAC: Add DDR3 LRDIMM entries to edac_mem_types x86, amd_nb: Add device IDs to NB tables for F15h M60h pci_ids: Add PCI device IDs for F15h M60h
Diffstat (limited to 'drivers/edac/amd64_edac.h')
-rw-r--r--drivers/edac/amd64_edac.h15
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 55fb5941c6d4..d8468c667925 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -162,10 +162,12 @@
162/* 162/*
163 * PCI-defined configuration space registers 163 * PCI-defined configuration space registers
164 */ 164 */
165#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
166#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
167#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 165#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
168#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 166#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
167#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
168#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
169#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
170#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
169#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531 171#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
170#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532 172#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
171#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581 173#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
@@ -221,6 +223,8 @@
221 223
222#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) 224#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
223 225
226#define DRAM_CONTROL 0x78
227
224#define DBAM0 0x80 228#define DBAM0 0x80
225#define DBAM1 0x180 229#define DBAM1 0x180
226 230
@@ -301,6 +305,7 @@ enum amd_families {
301 F10_CPUS, 305 F10_CPUS,
302 F15_CPUS, 306 F15_CPUS,
303 F15_M30H_CPUS, 307 F15_M30H_CPUS,
308 F15_M60H_CPUS,
304 F16_CPUS, 309 F16_CPUS,
305 F16_M30H_CPUS, 310 F16_M30H_CPUS,
306 NUM_FAMILIES, 311 NUM_FAMILIES,
@@ -379,6 +384,9 @@ struct amd64_pvt {
379 384
380 /* place to store error injection parameters prior to issue */ 385 /* place to store error injection parameters prior to issue */
381 struct error_injection injection; 386 struct error_injection injection;
387
388 /* cache the dram_type */
389 enum mem_type dram_type;
382}; 390};
383 391
384enum err_codes { 392enum err_codes {
@@ -480,7 +488,8 @@ struct low_ops {
480 int (*early_channel_count) (struct amd64_pvt *pvt); 488 int (*early_channel_count) (struct amd64_pvt *pvt);
481 void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr, 489 void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
482 struct err_info *); 490 struct err_info *);
483 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, unsigned cs_mode); 491 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct,
492 unsigned cs_mode, int cs_mask_nr);
484}; 493};
485 494
486struct amd64_family_type { 495struct amd64_family_type {