diff options
author | Borislav Petkov <borislav.petkov@amd.com> | 2011-01-07 10:26:49 -0500 |
---|---|---|
committer | Borislav Petkov <borislav.petkov@amd.com> | 2011-03-17 09:46:18 -0400 |
commit | 5980bb9cd88a3fa44cc5beab599f08fbc928b832 (patch) | |
tree | d5af45439240fb8e6535fc8a11c6f6903966c7ed /drivers/edac/amd64_edac.h | |
parent | bcd781f46a5f892ef2ae5843839849aa579fe096 (diff) |
amd64_edac: Cleanup old defines cruft
Remove unused defines, drop family names from define names.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac/amd64_edac.h')
-rw-r--r-- | drivers/edac/amd64_edac.h | 72 |
1 files changed, 9 insertions, 63 deletions
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 6c52736b09f2..04293306bedc 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h | |||
@@ -250,57 +250,11 @@ | |||
250 | #define NBCFG_CHIPKILL BIT(23) | 250 | #define NBCFG_CHIPKILL BIT(23) |
251 | #define NBCFG_ECC_ENABLE BIT(22) | 251 | #define NBCFG_ECC_ENABLE BIT(22) |
252 | 252 | ||
253 | #define K8_NBSL 0x48 | 253 | /* F3x48: NBSL */ |
254 | |||
255 | /* Family F10h: Normalized Extended Error Codes */ | ||
256 | #define F10_NBSL_EXT_ERR_RES 0x0 | ||
257 | #define F10_NBSL_EXT_ERR_ECC 0x8 | 254 | #define F10_NBSL_EXT_ERR_ECC 0x8 |
255 | #define NBSL_PP_OBS 0x2 | ||
258 | 256 | ||
259 | /* Next two are overloaded values */ | 257 | #define SCRCTRL 0x58 |
260 | #define F10_NBSL_EXT_ERR_LINK_PROTO 0xB | ||
261 | #define F10_NBSL_EXT_ERR_L3_PROTO 0xB | ||
262 | |||
263 | #define F10_NBSL_EXT_ERR_NB_ARRAY 0xC | ||
264 | #define F10_NBSL_EXT_ERR_DRAM_PARITY 0xD | ||
265 | #define F10_NBSL_EXT_ERR_LINK_RETRY 0xE | ||
266 | |||
267 | /* Next two are overloaded values */ | ||
268 | #define F10_NBSL_EXT_ERR_GART_WALK 0xF | ||
269 | #define F10_NBSL_EXT_ERR_DEV_WALK 0xF | ||
270 | |||
271 | /* 0x10 to 0x1B: Reserved */ | ||
272 | #define F10_NBSL_EXT_ERR_L3_DATA 0x1C | ||
273 | #define F10_NBSL_EXT_ERR_L3_TAG 0x1D | ||
274 | #define F10_NBSL_EXT_ERR_L3_LRU 0x1E | ||
275 | |||
276 | /* K8: Normalized Extended Error Codes */ | ||
277 | #define K8_NBSL_EXT_ERR_ECC 0x0 | ||
278 | #define K8_NBSL_EXT_ERR_CRC 0x1 | ||
279 | #define K8_NBSL_EXT_ERR_SYNC 0x2 | ||
280 | #define K8_NBSL_EXT_ERR_MST 0x3 | ||
281 | #define K8_NBSL_EXT_ERR_TGT 0x4 | ||
282 | #define K8_NBSL_EXT_ERR_GART 0x5 | ||
283 | #define K8_NBSL_EXT_ERR_RMW 0x6 | ||
284 | #define K8_NBSL_EXT_ERR_WDT 0x7 | ||
285 | #define K8_NBSL_EXT_ERR_CHIPKILL_ECC 0x8 | ||
286 | #define K8_NBSL_EXT_ERR_DRAM_PARITY 0xD | ||
287 | |||
288 | /* | ||
289 | * The following are for BUS type errors AFTER values have been normalized by | ||
290 | * shifting right | ||
291 | */ | ||
292 | #define K8_NBSL_PP_SRC 0x0 | ||
293 | #define K8_NBSL_PP_RES 0x1 | ||
294 | #define K8_NBSL_PP_OBS 0x2 | ||
295 | #define K8_NBSL_PP_GENERIC 0x3 | ||
296 | |||
297 | #define EXTRACT_ERR_CPU_MAP(x) ((x) & 0xF) | ||
298 | |||
299 | #define K8_NBEAL 0x50 | ||
300 | #define K8_NBEAH 0x54 | ||
301 | #define K8_SCRCTRL 0x58 | ||
302 | |||
303 | #define F10_NB_CFG_LOW 0x88 | ||
304 | 258 | ||
305 | #define F10_ONLINE_SPARE 0xB0 | 259 | #define F10_ONLINE_SPARE 0xB0 |
306 | #define F10_ONLINE_SPARE_SWAPDONE0(x) ((x) & BIT(1)) | 260 | #define F10_ONLINE_SPARE_SWAPDONE0(x) ((x) & BIT(1)) |
@@ -309,36 +263,28 @@ | |||
309 | #define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007) | 263 | #define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007) |
310 | 264 | ||
311 | #define F10_NB_ARRAY_ADDR 0xB8 | 265 | #define F10_NB_ARRAY_ADDR 0xB8 |
312 | 266 | #define F10_NB_ARRAY_DRAM_ECC BIT(31) | |
313 | #define F10_NB_ARRAY_DRAM_ECC 0x80000000 | ||
314 | 267 | ||
315 | /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ | 268 | /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ |
316 | #define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1) | 269 | #define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1) |
317 | 270 | ||
318 | #define F10_NB_ARRAY_DATA 0xBC | 271 | #define F10_NB_ARRAY_DATA 0xBC |
319 | |||
320 | #define SET_NB_DRAM_INJECTION_WRITE(word, bits) \ | 272 | #define SET_NB_DRAM_INJECTION_WRITE(word, bits) \ |
321 | (BIT(((word) & 0xF) + 20) | \ | 273 | (BIT(((word) & 0xF) + 20) | \ |
322 | BIT(17) | bits) | 274 | BIT(17) | bits) |
323 | |||
324 | #define SET_NB_DRAM_INJECTION_READ(word, bits) \ | 275 | #define SET_NB_DRAM_INJECTION_READ(word, bits) \ |
325 | (BIT(((word) & 0xF) + 20) | \ | 276 | (BIT(((word) & 0xF) + 20) | \ |
326 | BIT(16) | bits) | 277 | BIT(16) | bits) |
327 | 278 | ||
328 | #define K8_NBCAP 0xE8 | 279 | #define NBCAP 0xE8 |
329 | #define K8_NBCAP_CORES (BIT(12)|BIT(13)) | 280 | #define NBCAP_CHIPKILL BIT(4) |
330 | #define K8_NBCAP_CHIPKILL BIT(4) | 281 | #define NBCAP_SECDED BIT(3) |
331 | #define K8_NBCAP_SECDED BIT(3) | 282 | #define NBCAP_DCT_DUAL BIT(0) |
332 | #define K8_NBCAP_DCT_DUAL BIT(0) | ||
333 | 283 | ||
334 | #define EXT_NB_MCA_CFG 0x180 | 284 | #define EXT_NB_MCA_CFG 0x180 |
335 | 285 | ||
336 | /* MSRs */ | 286 | /* MSRs */ |
337 | #define K8_MSR_MCGCTL_NBE BIT(4) | 287 | #define MSR_MCGCTL_NBE BIT(4) |
338 | |||
339 | #define K8_MSR_MC4CTL 0x0410 | ||
340 | #define K8_MSR_MC4STAT 0x0411 | ||
341 | #define K8_MSR_MC4ADDR 0x0412 | ||
342 | 288 | ||
343 | /* AMD sets the first MC device at device ID 0x18. */ | 289 | /* AMD sets the first MC device at device ID 0x18. */ |
344 | static inline int get_node_id(struct pci_dev *pdev) | 290 | static inline int get_node_id(struct pci_dev *pdev) |