EDAC, AMD: carve out decoding of MCi_STATUS ErrorCode

This is the MCE error code from the MCi_STATUS banks, bits [15:0] which
describe what type of error was encountered: GART TLB, Memory or Bus
error. The semantics of those bits are identical across all MCE banks so
decode those separately, irrespectively of MCE type.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>

1 files changed, 0 insertions, 4 deletions

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index c81ca2cf8dc7..173dc4a84166 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2289,10 +2289,6 @@ static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci,
         u32 xec = EXT_ERROR_CODE(info->nbsl);
         int ecc_type = info->nbsh & (0x3 << 13);
 
-        pr_emerg(" Transaction type: %s(%s), %s, Cache Level: %s, %s\n",
-                 RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec), PP_MSG(ec));
-
-
         /* Bail early out if this was an 'observed' error */
         if (PP(ec) == K8_NBSL_PP_OBS)
                 return;