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authorBorislav Petkov <borislav.petkov@amd.com>2009-10-12 11:23:03 -0400
committerBorislav Petkov <borislav.petkov@amd.com>2009-10-16 12:51:22 -0400
commit4997811e3b9e4d6f37380701894f063c62f14929 (patch)
tree4d65d11db6e3ae02d900f1e431dde4d3a67e0963 /drivers/edac/amd64_edac.c
parent012abeea669ea49636cf952d13298bb68654146a (diff)
amd64_edac: fix DRAM base and limit extraction masks, v2
This is a proper fix as a follow-up to 66216a7 and 916d11b. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac/amd64_edac.c')
-rw-r--r--drivers/edac/amd64_edac.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 4f4ac82382f7..d4560d9d5a83 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1122,7 +1122,7 @@ static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
1122 debugf0("Reading K8_DRAM_BASE_LOW failed\n"); 1122 debugf0("Reading K8_DRAM_BASE_LOW failed\n");
1123 1123
1124 /* Extract parts into separate data entries */ 1124 /* Extract parts into separate data entries */
1125 pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 24; 1125 pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8;
1126 pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7; 1126 pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7;
1127 pvt->dram_rw_en[dram] = (low & 0x3); 1127 pvt->dram_rw_en[dram] = (low & 0x3);
1128 1128
@@ -1135,7 +1135,7 @@ static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
1135 * Extract parts into separate data entries. Limit is the HIGHEST memory 1135 * Extract parts into separate data entries. Limit is the HIGHEST memory
1136 * location of the region, so lower 24 bits need to be all ones 1136 * location of the region, so lower 24 bits need to be all ones
1137 */ 1137 */
1138 pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 24) | 0x00FFFFFF; 1138 pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF;
1139 pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7; 1139 pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7;
1140 pvt->dram_DstNode[dram] = (low & 0x7); 1140 pvt->dram_DstNode[dram] = (low & 0x7);
1141} 1141}
@@ -1369,7 +1369,7 @@ static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
1369 pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7; 1369 pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7;
1370 1370
1371 pvt->dram_base[dram] = (((u64)high_base & 0x000000FF) << 40) | 1371 pvt->dram_base[dram] = (((u64)high_base & 0x000000FF) << 40) |
1372 (((u64)low_base & 0xFFFF0000) << 24); 1372 (((u64)low_base & 0xFFFF0000) << 8);
1373 1373
1374 low_offset = K8_DRAM_LIMIT_LOW + (dram << 3); 1374 low_offset = K8_DRAM_LIMIT_LOW + (dram << 3);
1375 high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3); 1375 high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3);
@@ -1391,7 +1391,7 @@ static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
1391 * memory location of the region, so low 24 bits need to be all ones. 1391 * memory location of the region, so low 24 bits need to be all ones.
1392 */ 1392 */
1393 pvt->dram_limit[dram] = (((u64)high_limit & 0x000000FF) << 40) | 1393 pvt->dram_limit[dram] = (((u64)high_limit & 0x000000FF) << 40) |
1394 (((u64) low_limit & 0xFFFF0000) << 24) | 1394 (((u64) low_limit & 0xFFFF0000) << 8) |
1395 0x00FFFFFF; 1395 0x00FFFFFF;
1396} 1396}
1397 1397