aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/edac/amd64_edac.c
diff options
context:
space:
mode:
authorBorislav Petkov <borislav.petkov@amd.com>2011-09-19 11:34:45 -0400
committerBorislav Petkov <borislav.petkov@amd.com>2011-10-06 06:34:05 -0400
commit73ba85937b2a07b6401ba0b7ca06a112762de9f7 (patch)
treef4905768cf9cc469b79e92a3c7cf9dec2c6079b1 /drivers/edac/amd64_edac.c
parentb0b07a2bd4fbb6198d4e7142337214eeb77c417a (diff)
amd64_edac: Add a fix for Erratum 505
When accessing the scrub rate control register (F3x58) on F15h, the DRAM controller selector (F1x10C[DctCfgSel]) has to point to DCT0 so that the scrub rate configuration can take effect. See Erratum 505 in the AMD F15h revision guide for more details. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac/amd64_edac.c')
-rw-r--r--drivers/edac/amd64_edac.c27
1 files changed, 22 insertions, 5 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 9bf0b6228529..367756a48ebe 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -114,10 +114,22 @@ static int f10_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
114 return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func); 114 return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
115} 115}
116 116
117/*
118 * Select DCT to which PCI cfg accesses are routed
119 */
120static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct)
121{
122 u32 reg = 0;
123
124 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, &reg);
125 reg &= 0xfffffffe;
126 reg |= dct;
127 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
128}
129
117static int f15_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val, 130static int f15_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
118 const char *func) 131 const char *func)
119{ 132{
120 u32 reg = 0;
121 u8 dct = 0; 133 u8 dct = 0;
122 134
123 if (addr >= 0x140 && addr <= 0x1a0) { 135 if (addr >= 0x140 && addr <= 0x1a0) {
@@ -125,10 +137,7 @@ static int f15_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
125 addr -= 0x100; 137 addr -= 0x100;
126 } 138 }
127 139
128 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, &reg); 140 f15h_select_dct(pvt, dct);
129 reg &= 0xfffffffe;
130 reg |= dct;
131 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
132 141
133 return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func); 142 return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
134} 143}
@@ -198,6 +207,10 @@ static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
198 if (boot_cpu_data.x86 == 0xf) 207 if (boot_cpu_data.x86 == 0xf)
199 min_scrubrate = 0x0; 208 min_scrubrate = 0x0;
200 209
210 /* F15h Erratum #505 */
211 if (boot_cpu_data.x86 == 0x15)
212 f15h_select_dct(pvt, 0);
213
201 return __amd64_set_scrub_rate(pvt->F3, bw, min_scrubrate); 214 return __amd64_set_scrub_rate(pvt->F3, bw, min_scrubrate);
202} 215}
203 216
@@ -207,6 +220,10 @@ static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
207 u32 scrubval = 0; 220 u32 scrubval = 0;
208 int i, retval = -EINVAL; 221 int i, retval = -EINVAL;
209 222
223 /* F15h Erratum #505 */
224 if (boot_cpu_data.x86 == 0x15)
225 f15h_select_dct(pvt, 0);
226
210 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); 227 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
211 228
212 scrubval = scrubval & 0x001F; 229 scrubval = scrubval & 0x001F;