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authorDoug Thompson <dougthompson@xmission.com>2009-04-27 10:14:52 -0400
committerBorislav Petkov <borislav.petkov@amd.com>2009-06-10 06:18:54 -0400
commitddff876d2022c5e06509f6535bc4fd61c4d6ffd6 (patch)
tree228ebfefd1a2f1a35f3058fa610557432182f5c5 /drivers/edac/amd64_edac.c
parent94be4bff21990674ac418c970c708a1a01cf709f (diff)
amd64_edac: add k8-specific methods
Borislav: - fix/cleanup/move comments - fix function return value patterns - cleanup debug calls Reviewed-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac/amd64_edac.c')
-rw-r--r--drivers/edac/amd64_edac.c173
1 files changed, 173 insertions, 0 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 5ec44a440d65..24c031f79756 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1013,3 +1013,176 @@ static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt)
1013 return type; 1013 return type;
1014} 1014}
1015 1015
1016/*
1017 * Read the DRAM Configuration Low register. It differs between CG, D & E revs
1018 * and the later RevF memory controllers (DDR vs DDR2)
1019 *
1020 * Return:
1021 * number of memory channels in operation
1022 * Pass back:
1023 * contents of the DCL0_LOW register
1024 */
1025static int k8_early_channel_count(struct amd64_pvt *pvt)
1026{
1027 int flag, err = 0;
1028
1029 err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0);
1030 if (err)
1031 return err;
1032
1033 if ((boot_cpu_data.x86_model >> 4) >= OPTERON_CPU_REV_F) {
1034 /* RevF (NPT) and later */
1035 flag = pvt->dclr0 & F10_WIDTH_128;
1036 } else {
1037 /* RevE and earlier */
1038 flag = pvt->dclr0 & REVE_WIDTH_128;
1039 }
1040
1041 /* not used */
1042 pvt->dclr1 = 0;
1043
1044 return (flag) ? 2 : 1;
1045}
1046
1047/* extract the ERROR ADDRESS for the K8 CPUs */
1048static u64 k8_get_error_address(struct mem_ctl_info *mci,
1049 struct amd64_error_info_regs *info)
1050{
1051 return (((u64) (info->nbeah & 0xff)) << 32) +
1052 (info->nbeal & ~0x03);
1053}
1054
1055/*
1056 * Read the Base and Limit registers for K8 based Memory controllers; extract
1057 * fields from the 'raw' reg into separate data fields
1058 *
1059 * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN
1060 */
1061static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
1062{
1063 u32 low;
1064 u32 off = dram << 3; /* 8 bytes between DRAM entries */
1065 int err;
1066
1067 err = pci_read_config_dword(pvt->addr_f1_ctl,
1068 K8_DRAM_BASE_LOW + off, &low);
1069 if (err)
1070 debugf0("Reading K8_DRAM_BASE_LOW failed\n");
1071
1072 /* Extract parts into separate data entries */
1073 pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8;
1074 pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7;
1075 pvt->dram_rw_en[dram] = (low & 0x3);
1076
1077 err = pci_read_config_dword(pvt->addr_f1_ctl,
1078 K8_DRAM_LIMIT_LOW + off, &low);
1079 if (err)
1080 debugf0("Reading K8_DRAM_LIMIT_LOW failed\n");
1081
1082 /*
1083 * Extract parts into separate data entries. Limit is the HIGHEST memory
1084 * location of the region, so lower 24 bits need to be all ones
1085 */
1086 pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF;
1087 pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7;
1088 pvt->dram_DstNode[dram] = (low & 0x7);
1089}
1090
1091static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
1092 struct amd64_error_info_regs *info,
1093 u64 SystemAddress)
1094{
1095 struct mem_ctl_info *src_mci;
1096 unsigned short syndrome;
1097 int channel, csrow;
1098 u32 page, offset;
1099
1100 /* Extract the syndrome parts and form a 16-bit syndrome */
1101 syndrome = EXTRACT_HIGH_SYNDROME(info->nbsl) << 8;
1102 syndrome |= EXTRACT_LOW_SYNDROME(info->nbsh);
1103
1104 /* CHIPKILL enabled */
1105 if (info->nbcfg & K8_NBCFG_CHIPKILL) {
1106 channel = get_channel_from_ecc_syndrome(syndrome);
1107 if (channel < 0) {
1108 /*
1109 * Syndrome didn't map, so we don't know which of the
1110 * 2 DIMMs is in error. So we need to ID 'both' of them
1111 * as suspect.
1112 */
1113 amd64_mc_printk(mci, KERN_WARNING,
1114 "unknown syndrome 0x%x - possible error "
1115 "reporting race\n", syndrome);
1116 edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
1117 return;
1118 }
1119 } else {
1120 /*
1121 * non-chipkill ecc mode
1122 *
1123 * The k8 documentation is unclear about how to determine the
1124 * channel number when using non-chipkill memory. This method
1125 * was obtained from email communication with someone at AMD.
1126 * (Wish the email was placed in this comment - norsk)
1127 */
1128 channel = ((SystemAddress & BIT(3)) != 0);
1129 }
1130
1131 /*
1132 * Find out which node the error address belongs to. This may be
1133 * different from the node that detected the error.
1134 */
1135 src_mci = find_mc_by_sys_addr(mci, SystemAddress);
1136 if (src_mci) {
1137 amd64_mc_printk(mci, KERN_ERR,
1138 "failed to map error address 0x%lx to a node\n",
1139 (unsigned long)SystemAddress);
1140 edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
1141 return;
1142 }
1143
1144 /* Now map the SystemAddress to a CSROW */
1145 csrow = sys_addr_to_csrow(src_mci, SystemAddress);
1146 if (csrow < 0) {
1147 edac_mc_handle_ce_no_info(src_mci, EDAC_MOD_STR);
1148 } else {
1149 error_address_to_page_and_offset(SystemAddress, &page, &offset);
1150
1151 edac_mc_handle_ce(src_mci, page, offset, syndrome, csrow,
1152 channel, EDAC_MOD_STR);
1153 }
1154}
1155
1156/*
1157 * determrine the number of PAGES in for this DIMM's size based on its DRAM
1158 * Address Mapping.
1159 *
1160 * First step is to calc the number of bits to shift a value of 1 left to
1161 * indicate show many pages. Start with the DBAM value as the starting bits,
1162 * then proceed to adjust those shift bits, based on CPU rev and the table.
1163 * See BKDG on the DBAM
1164 */
1165static int k8_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map)
1166{
1167 int nr_pages;
1168
1169 if (pvt->ext_model >= OPTERON_CPU_REV_F) {
1170 nr_pages = 1 << (revf_quad_ddr2_shift[dram_map] - PAGE_SHIFT);
1171 } else {
1172 /*
1173 * RevE and less section; this line is tricky. It collapses the
1174 * table used by RevD and later to one that matches revisions CG
1175 * and earlier.
1176 */
1177 dram_map -= (pvt->ext_model >= OPTERON_CPU_REV_D) ?
1178 (dram_map > 8 ? 4 : (dram_map > 5 ?
1179 3 : (dram_map > 2 ? 1 : 0))) : 0;
1180
1181 /* 25 shift is 32MiB minimum DIMM size in RevE and prior */
1182 nr_pages = 1 << (dram_map + 25 - PAGE_SHIFT);
1183 }
1184
1185 return nr_pages;
1186}
1187
1188