diff options
author | Arthur Jones <ajones@riverbed.com> | 2008-07-25 04:49:04 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-25 13:53:48 -0400 |
commit | 8f421c595a9145959d8aab09172743132abdffdb (patch) | |
tree | 05c374ad506a47c127007dcab4dc7018b7f93c1c /drivers/edac/Kconfig | |
parent | 48e90761b570ff57f58b726229d229729949c5bb (diff) |
edac: i5100 new intel chipset driver
Preliminary support for the Intel 5100 MCH. CE and UE errors are reported
along with the current DIMM label information and other memory parameters.
Reasons why this is preliminary:
1) This chip has 2 independent memory controllers which, for best
perforance, use interleaved accesses to the DDR2 memory. This
architecture does not map very well to the current edac data structures
which depend on symmetric channel access to the interleaved data.
Without core changes, the best I could do for now is to map both memory
controllers to different csrows (first all ranks of controller 0, then
all ranks of controller 1). Someone much more familiar with the edac
core than I will probably need to come up with a more general data
structure to handle the interleaving and de-interleaving of the two
memory controllers.
2) I have not yet tackled the de-interleaving of the rank/controller
address space into the physical address space of the CPU. There is
nothing fundamentally missing, it is just ending up to be a lot of
code, and I'd rather keep it separate for now, esp since it doesn't
work yet...
3) The code depends on a particular i5100 chip select to DIMM mainboard
chip select mapping. This mapping seems obvious to me in order to
support dual and single ranked memory, but it is not unique and DIMM
labels could be wrong on other mainboards. There is no way to query
this mapping that I know of.
4) The code requires that the i5100 is in 32GB mode. Only 4 ranks per
controller, 2 ranks per DIMM are supported. I do not have hardware
(nor do I expect to have hardware anytime soon) for the 48GB (6 ranks
per controller) mode.
5) The serial presence detect code should be broken out into a "real"
i2c driver so that decode-dimms.pl can work.
Signed-off-by: Arthur Jones <ajones@riverbed.com>
Signed-off-by: Doug Thompson <dougthompson@xmission.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/edac/Kconfig')
-rw-r--r-- | drivers/edac/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 6e6c3c4aea6b..5a11e3cbcae2 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig | |||
@@ -123,6 +123,13 @@ config EDAC_I5000 | |||
123 | Support for error detection and correction the Intel | 123 | Support for error detection and correction the Intel |
124 | Greekcreek/Blackford chipsets. | 124 | Greekcreek/Blackford chipsets. |
125 | 125 | ||
126 | config EDAC_I5100 | ||
127 | tristate "Intel San Clemente MCH" | ||
128 | depends on EDAC_MM_EDAC && X86 && PCI | ||
129 | help | ||
130 | Support for error detection and correction the Intel | ||
131 | San Clemente MCH. | ||
132 | |||
126 | config EDAC_MPC85XX | 133 | config EDAC_MPC85XX |
127 | tristate "Freescale MPC85xx" | 134 | tristate "Freescale MPC85xx" |
128 | depends on EDAC_MM_EDAC && FSL_SOC && MPC85xx | 135 | depends on EDAC_MM_EDAC && FSL_SOC && MPC85xx |