dw_dmac: Allow src/dst msize & flow controller to be configured at runtime

Msize or Burst Size is peripheral dependent in case of prep_slave_sg and
cyclic_prep transfers, and in case of memcpy transfers it is platform dependent.
So msize configuration must come from platform data.

Also some peripherals (ex: JPEG), need to be flow controller for dma transfers,
so this information in case of slave_sg & cyclic_prep transfers must come from
platform data.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

2 files changed, 9 insertions, 6 deletions

diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index 318a342fc7ec..90ea08a53d62 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -36,9 +36,11 @@
                 struct dw_dma_slave *__slave = (private);       \
                 int dms = __slave ? __slave->dst_master : 0;    \
                 int sms = __slave ? __slave->src_master : 1;    \
+                u8 smsize = __slave ? __slave->src_msize : 0;   \
+                u8 dmsize = __slave ? __slave->dst_msize : 0;   \
                                                                 \
-                (DWC_CTLL_DST_MSIZE(0)                          \
-                 | DWC_CTLL_SRC_MSIZE(0)                        \
+                (DWC_CTLL_DST_MSIZE(dmsize)                     \
+                 | DWC_CTLL_SRC_MSIZE(smsize)                   \
                  | DWC_CTLL_LLP_D_EN                            \
                  | DWC_CTLL_LLP_S_EN                            \
                  | DWC_CTLL_DMS(dms)                            \
@@ -683,7 +685,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
                                 | DWC_CTLL_DST_WIDTH(reg_width)
                                 | DWC_CTLL_DST_FIX
                                 | DWC_CTLL_SRC_INC
-                                | DWC_CTLL_FC_M2P);
+                                | DWC_CTLL_FC(dws->fc));
                 reg = dws->tx_reg;
                 for_each_sg(sgl, sg, sg_len, i) {
                         struct dw_desc  *desc;
@@ -728,7 +730,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
                                 | DWC_CTLL_SRC_WIDTH(reg_width)
                                 | DWC_CTLL_DST_INC
                                 | DWC_CTLL_SRC_FIX
-                                | DWC_CTLL_FC_P2M);
+                                | DWC_CTLL_FC(dws->fc));
 
                 reg = dws->rx_reg;
                 for_each_sg(sgl, sg, sg_len, i) {
@@ -1146,7 +1148,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
                                         | DWC_CTLL_SRC_WIDTH(reg_width)
                                         | DWC_CTLL_DST_FIX
                                         | DWC_CTLL_SRC_INC
-                                        | DWC_CTLL_FC_M2P
+                                        | DWC_CTLL_FC(dws->fc)
                                         | DWC_CTLL_INT_EN);
                         break;
                 case DMA_FROM_DEVICE:
@@ -1157,7 +1159,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
                                         | DWC_CTLL_DST_WIDTH(reg_width)
                                         | DWC_CTLL_DST_INC
                                         | DWC_CTLL_SRC_FIX
-                                        | DWC_CTLL_FC_P2M
+                                        | DWC_CTLL_FC(dws->fc)
                                         | DWC_CTLL_INT_EN);
                         break;
                 default:
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h
index 6a8e6d35f359..9a32964bf795 100644
--- a/drivers/dma/dw_dmac_regs.h
+++ b/drivers/dma/dw_dmac_regs.h
@@ -86,6 +86,7 @@ struct dw_dma_regs {
 #define DWC_CTLL_SRC_MSIZE(n)   ((n)<<14)
 #define DWC_CTLL_S_GATH_EN      (1 << 17)       /* src gather, !FIX */
 #define DWC_CTLL_D_SCAT_EN      (1 << 18)       /* dst scatter, !FIX */
+#define DWC_CTLL_FC(n)          ((n) << 20)
 #define DWC_CTLL_FC_M2M         (0 << 20)       /* mem-to-mem */
 #define DWC_CTLL_FC_M2P         (1 << 20)       /* mem-to-periph */
 #define DWC_CTLL_FC_P2M         (2 << 20)       /* periph-to-mem */