diff options
author | Shawn Guo <shawn.guo@linaro.org> | 2012-05-07 02:14:08 -0400 |
---|---|---|
committer | Shawn Guo <shawn.guo@linaro.org> | 2012-05-12 01:32:17 -0400 |
commit | bb11fb63fc2e5d1092f17d91790bb4aede6d3ef2 (patch) | |
tree | 8b06d7e8e71588aaeed45f13b0be1352bf0d4286 /drivers/dma | |
parent | f5b7efccdb057a2cc8ee32c83d2f034e494a1f4a (diff) |
dma: mxs-dma: let dma_is_apbh and apbh_is_old take parameter
Let macros dma_is_apbh and apbh_is_old take mxs_dma as parameter
to make the code easy to read.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'drivers/dma')
-rw-r--r-- | drivers/dma/mxs-dma.c | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c index bd278187fd81..c93f9fa08caf 100644 --- a/drivers/dma/mxs-dma.c +++ b/drivers/dma/mxs-dma.c | |||
@@ -38,10 +38,10 @@ | |||
38 | 38 | ||
39 | #define MXS_DMA_APBH 0 | 39 | #define MXS_DMA_APBH 0 |
40 | #define MXS_DMA_APBX 1 | 40 | #define MXS_DMA_APBX 1 |
41 | #define dma_is_apbh() (mxs_dma->dev_id == MXS_DMA_APBH) | 41 | #define dma_is_apbh(mxs_dma) ((mxs_dma)->dev_id == MXS_DMA_APBH) |
42 | 42 | ||
43 | #define APBH_VERSION_LATEST 3 | 43 | #define APBH_VERSION_LATEST 3 |
44 | #define apbh_is_old() (mxs_dma->version < APBH_VERSION_LATEST) | 44 | #define apbh_is_old(mxs_dma) ((mxs_dma)->version < APBH_VERSION_LATEST) |
45 | 45 | ||
46 | #define HW_APBHX_CTRL0 0x000 | 46 | #define HW_APBHX_CTRL0 0x000 |
47 | #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) | 47 | #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29) |
@@ -54,10 +54,14 @@ | |||
54 | #define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800) | 54 | #define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800) |
55 | #define HW_APBX_VERSION 0x800 | 55 | #define HW_APBX_VERSION 0x800 |
56 | #define BP_APBHX_VERSION_MAJOR 24 | 56 | #define BP_APBHX_VERSION_MAJOR 24 |
57 | #define HW_APBHX_CHn_NXTCMDAR(n) \ | 57 | /* |
58 | (((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70) | 58 | * The offset of NXTCMDAR register is different per both dma type and version, |
59 | #define HW_APBHX_CHn_SEMA(n) \ | 59 | * while stride for each channel is all the same 0x70. |
60 | (((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70) | 60 | */ |
61 | #define HW_APBHX_CHn_NXTCMDAR(d, n) \ | ||
62 | (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70) | ||
63 | #define HW_APBHX_CHn_SEMA(d, n) \ | ||
64 | (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70) | ||
61 | 65 | ||
62 | /* | 66 | /* |
63 | * ccw bits definitions | 67 | * ccw bits definitions |
@@ -136,7 +140,7 @@ static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan) | |||
136 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; | 140 | struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; |
137 | int chan_id = mxs_chan->chan.chan_id; | 141 | int chan_id = mxs_chan->chan.chan_id; |
138 | 142 | ||
139 | if (dma_is_apbh() && apbh_is_old()) | 143 | if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) |
140 | writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), | 144 | writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), |
141 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); | 145 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); |
142 | else | 146 | else |
@@ -151,10 +155,10 @@ static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan) | |||
151 | 155 | ||
152 | /* set cmd_addr up */ | 156 | /* set cmd_addr up */ |
153 | writel(mxs_chan->ccw_phys, | 157 | writel(mxs_chan->ccw_phys, |
154 | mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id)); | 158 | mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id)); |
155 | 159 | ||
156 | /* write 1 to SEMA to kick off the channel */ | 160 | /* write 1 to SEMA to kick off the channel */ |
157 | writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id)); | 161 | writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id)); |
158 | } | 162 | } |
159 | 163 | ||
160 | static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan) | 164 | static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan) |
@@ -168,7 +172,7 @@ static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan) | |||
168 | int chan_id = mxs_chan->chan.chan_id; | 172 | int chan_id = mxs_chan->chan.chan_id; |
169 | 173 | ||
170 | /* freeze the channel */ | 174 | /* freeze the channel */ |
171 | if (dma_is_apbh() && apbh_is_old()) | 175 | if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) |
172 | writel(1 << chan_id, | 176 | writel(1 << chan_id, |
173 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); | 177 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); |
174 | else | 178 | else |
@@ -184,7 +188,7 @@ static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan) | |||
184 | int chan_id = mxs_chan->chan.chan_id; | 188 | int chan_id = mxs_chan->chan.chan_id; |
185 | 189 | ||
186 | /* unfreeze the channel */ | 190 | /* unfreeze the channel */ |
187 | if (dma_is_apbh() && apbh_is_old()) | 191 | if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) |
188 | writel(1 << chan_id, | 192 | writel(1 << chan_id, |
189 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR); | 193 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR); |
190 | else | 194 | else |
@@ -578,7 +582,7 @@ static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) | |||
578 | BP_APBHX_VERSION_MAJOR; | 582 | BP_APBHX_VERSION_MAJOR; |
579 | 583 | ||
580 | /* enable apbh burst */ | 584 | /* enable apbh burst */ |
581 | if (dma_is_apbh()) { | 585 | if (dma_is_apbh(mxs_dma)) { |
582 | writel(BM_APBH_CTRL0_APB_BURST_EN, | 586 | writel(BM_APBH_CTRL0_APB_BURST_EN, |
583 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); | 587 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); |
584 | writel(BM_APBH_CTRL0_APB_BURST8_EN, | 588 | writel(BM_APBH_CTRL0_APB_BURST8_EN, |