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authorJonas Aaberg <jonas.aberg@stericsson.com>2010-08-09 08:08:18 -0400
committerDan Williams <dan.j.williams@intel.com>2010-09-22 17:53:45 -0400
commit3ae0267fd569c2007235fb80cfe3b4a4c54c8f4b (patch)
tree1d300eead20bff1737b3e79c48ee0bd0640ea0dd /drivers/dma
parent0246e77b4d374bb37aa08c3fcadad20012e85ea0 (diff)
DMAENGINE: ste_dma40: removed a few magic numbers
Make sure to extract the revision field explicitly and document what bits are being accessed here without magic numbers. Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma')
-rw-r--r--drivers/dma/ste_dma40.c18
-rw-r--r--drivers/dma/ste_dma40_ll.h3
2 files changed, 15 insertions, 6 deletions
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index a6a7d66df77a..c042103d7c0d 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -41,7 +41,7 @@
41#define D40_ALLOC_LOG_FREE 0 41#define D40_ALLOC_LOG_FREE 0
42 42
43/* Hardware designer of the block */ 43/* Hardware designer of the block */
44#define D40_PERIPHID2_DESIGNER 0x8 44#define D40_HW_DESIGNER 0x8
45 45
46/** 46/**
47 * enum 40_command - The different commands and/or statuses. 47 * enum 40_command - The different commands and/or statuses.
@@ -2438,6 +2438,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2438 int num_phy_chans; 2438 int num_phy_chans;
2439 int i; 2439 int i;
2440 u32 val; 2440 u32 val;
2441 u32 rev;
2441 2442
2442 clk = clk_get(&pdev->dev, NULL); 2443 clk = clk_get(&pdev->dev, NULL);
2443 2444
@@ -2476,21 +2477,26 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2476 } 2477 }
2477 } 2478 }
2478 2479
2479 /* Get silicon revision */ 2480 /* Get silicon revision and designer */
2480 val = readl(virtbase + D40_DREG_PERIPHID2); 2481 val = readl(virtbase + D40_DREG_PERIPHID2);
2481 2482
2482 if ((val & 0xf) != D40_PERIPHID2_DESIGNER) { 2483 if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) !=
2484 D40_HW_DESIGNER) {
2483 dev_err(&pdev->dev, 2485 dev_err(&pdev->dev,
2484 "[%s] Unknown designer! Got %x wanted %x\n", 2486 "[%s] Unknown designer! Got %x wanted %x\n",
2485 __func__, val & 0xf, D40_PERIPHID2_DESIGNER); 2487 __func__, val & D40_DREG_PERIPHID2_DESIGNER_MASK,
2488 D40_HW_DESIGNER);
2486 goto failure; 2489 goto failure;
2487 } 2490 }
2488 2491
2492 rev = (val & D40_DREG_PERIPHID2_REV_MASK) >>
2493 D40_DREG_PERIPHID2_REV_POS;
2494
2489 /* The number of physical channels on this HW */ 2495 /* The number of physical channels on this HW */
2490 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4; 2496 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2491 2497
2492 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n", 2498 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
2493 (val >> 4) & 0xf, res->start); 2499 rev, res->start);
2494 2500
2495 plat_data = pdev->dev.platform_data; 2501 plat_data = pdev->dev.platform_data;
2496 2502
@@ -2512,7 +2518,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2512 goto failure; 2518 goto failure;
2513 } 2519 }
2514 2520
2515 base->rev = (val >> 4) & 0xf; 2521 base->rev = rev;
2516 base->clk = clk; 2522 base->clk = clk;
2517 base->num_phy_chans = num_phy_chans; 2523 base->num_phy_chans = num_phy_chans;
2518 base->num_log_chans = num_log_chans; 2524 base->num_log_chans = num_log_chans;
diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h
index 0c468c310c18..7a6acecfccd5 100644
--- a/drivers/dma/ste_dma40_ll.h
+++ b/drivers/dma/ste_dma40_ll.h
@@ -163,6 +163,9 @@
163#define D40_DREG_PERIPHID0 0xFE0 163#define D40_DREG_PERIPHID0 0xFE0
164#define D40_DREG_PERIPHID1 0xFE4 164#define D40_DREG_PERIPHID1 0xFE4
165#define D40_DREG_PERIPHID2 0xFE8 165#define D40_DREG_PERIPHID2 0xFE8
166#define D40_DREG_PERIPHID2_REV_POS 4
167#define D40_DREG_PERIPHID2_REV_MASK (0xf << D40_DREG_PERIPHID2_REV_POS)
168#define D40_DREG_PERIPHID2_DESIGNER_MASK 0xf
166#define D40_DREG_PERIPHID3 0xFEC 169#define D40_DREG_PERIPHID3 0xFEC
167#define D40_DREG_CELLID0 0xFF0 170#define D40_DREG_CELLID0 0xFF0
168#define D40_DREG_CELLID1 0xFF4 171#define D40_DREG_CELLID1 0xFF4